Carroll, B. D., & Gieser, S. N., & Levine, D. (2014, June), A Hierarchical Project-Based Introduction to Digital Logic Design Course  Paper presented at 2014 ASEE Annual Conference & Exposition, Indianapolis, Indiana. 10.18260/1-2--19946

\bibitem{asee_peer_19946}
  Carroll, B. D., \& Gieser, S. N., \& Levine, D. (2014, June), \emph{A Hierarchical Project-Based Introduction to Digital Logic Design Course}
  Paper presented at 2014 ASEE Annual Conference \& Exposition, Indianapolis, Indiana.
  10.18260/1-2--19946

Bill D Carroll P.E., Shawn N Gieser, and David Levine.  "A Hierarchical Project-Based Introduction to Digital Logic Design Course".  2014 ASEE Annual Conference & Exposition, Indianapolis, Indiana, 2014, June.  ASEE Conferences, 2014.  https://peer.asee.org/19946 Internet.  26 May, 2024

\bibitem{asee_peer_19946}
  Bill D Carroll P.E., Shawn N Gieser, and David Levine.
  "A Hierarchical Project-Based Introduction to Digital Logic Design Course".
  \emph{2014 ASEE Annual Conference \& Exposition, Indianapolis, Indiana, 2014, June}.
  ASEE Conferences, 2014.
  https://peer.asee.org/19946 Internet.  26 May, 2024

@INPROCEEDINGS{asee_peer_19946
author = "Bill D Carroll P.E., Shawn N Gieser, and David Levine"
title = "A Hierarchical Project-Based Introduction to Digital Logic Design Course"
booktitle = "2014 ASEE Annual Conference \& Exposition"
year = "2014"
month = "June"
address = "Indianapolis, Indiana"
publisher = "ASEE Conferences"
note = {https://peer.asee.org/19946}
number = {10.18260/1-2--19946}
}

TY  - CPAPER
AB  -   A Hierarchical Project-Based Introduction to Digital Logic Design CourseCourses in digital logic design are required by virtually all electrical engineering and computerengineering programs and by many computer science programs. Credit hour reduction mandatesoften constrain coverage to a single required course. Typically, logic design courses coverfundamentals in lectures with applications and technology being covered in a laboratory setting.Also, these courses are well suited to address ABET student outcome requirements. However,coordinating the lectures with the laboratories can be challenging, and students often miss theconnection between fundamentals and the applications. Our introduction to digital logic coursehas been updated and restructured over the past two years to address these and other issues.This paper covers details of the restructured course and discusses lessons learned. Assessment isongoing and will be presented in the paper and conference presentation. For the past severalyears, the course has addressed ABET/EAC student outcomes (a), (c), and (k) with keyassignments and a design project at the end of the course. The project was necessarily limited inscope due to time constraints, student preparation, and the absence of lab resources to implementthe project. Students were required to design and simulate their project but not to implementand test it.The restructured course features a project that runs throughout the semester and culminates withimplementation and testing on a field-programmable gate array (FPGA). A hierarchical designapproach is used so that the results of weekly or biweekly lab exercises can be integrated for thefinal design. The project being incorporated in the course is the design of a basic four-bitcomputer processing unit. Students design and implement a four-function ALU fromcombinational logic during the first third of the course. The middle-third of the course focuseson the design and implementation of the various registers and counters needed in the processor.The final third covers design of the control unit and integration of the previously designedcomponents. All design work is captured and simulated using the Altera Quartus II designsoftware and then implement using an Altera Cyclone II FPGA on an Altera DE-1 developmentboard. Some components are also implemented using basic integrated circuits on solder-lessbreadboards. This gives students hands-on experience constructing, testing, and debuggingcircuits that cannot be gained from FPGA implementation. A written project report is required atthe end of the semester.Laboratory assignments are introduced during lectures. This provides better linkage between thefundamentals being covered in the lectures and the applications and hands-on laboratoryexperiences. This approach also allows for an earlier inclusion of interesting and meaningfullaboratory exercises.In summary, the restructured introduction to digital logic course incorporates a semester-longdesign and implementation project that follows a hierarchical design approach. This is enabledby the use of powerful design capture and simulation software during design and easy to useFPGA technology for implementation and testing. Emphasis on fundamentals is maintained byclose linkage of lecture and hands-on laboratory exercises.
AU  - Bill D Carroll P.E.
AU  - Shawn N Gieser
AU  - David Levine
CY  - Indianapolis, Indiana
DA  - 2014/06/15
PB  - ASEE Conferences
TI  - A Hierarchical Project-Based Introduction to Digital Logic Design Course
UR  - https://peer.asee.org/19946
DO  - 10.18260/1-2--19946
ER  -