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students more on active learning.Modelsim waveform simulationThe Modelsim tool is one of the industry level verification and simulation tools for testingVerilog HDL designs. The Figure 7 below shows the Verilog design and the related Modelsimtesting commands for 3-stage right shift registers. When the parallel load signal PL is activehigh, after rising edge of clock, the 3-bit data vector p will be loaded into the 3-bit D Flip-Floptype of register bank q. When PL is not active, the data inside the 3-bit registers will shift fromthe left to the right. 7 © American Society for Engineering Education, 2015
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