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Does Logic Synthesis Visualization Excite EETs?

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Conference

2011 ASEE Annual Conference & Exposition

Location

Vancouver, BC

Publication Date

June 26, 2011

Start Date

June 26, 2011

End Date

June 29, 2011

ISSN

2153-5965

Conference Session

Factors Affecting Student Performance

Tagged Division

Engineering Technology

Page Count

10

Page Numbers

22.511.1 - 22.511.10

DOI

10.18260/1-2--17792

Permanent URL

https://peer.asee.org/17792

Download Count

49

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Paper Authors

biography

Maddumage Karunaratne University of Pittsburgh, Johnstown

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Dr. Maddumage Karunaratne is an Associate Professor and the Head of the Electrical Engineering Technology department at the University of Pittsburgh, Johnstown, PA. The department offers two undergraduate degrees in Electrical Engineering Technology and Computer Engineering Technology. Dr. Karunaratne earned a Bachelor of Science degree from the University of Moratuwa (Sri Lanka), a Master of Science from the University of Mississippi (Oxford), and a Ph.D. from the University of Arizona (Tucson).

Before joining academia, he gained fourteen years of extensive industry experience working in the semiconductor industry in software development, application engineering, design, testing and verification of digital integrated circuits. He has taught electrical and general engineering technology classes at Pitt, Johnstown for the last seven years.

His research and teaching interests include Semiconductor circuit Testing and Verification, Low Power Design Analysis, Digital and Embedded Systems, Electromagnetic Wave Scattering, and IC Design Automation Software development.

He can be reached at maddu@pitt.edu or at
225 Engineering and Science Building,
University of Pittsburgh at Johnstown,
Johnstown, PA 15904

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Abstract

Does Logic Synthesis Visualization Excite EETs?Abstract :Based on industry trends and recent advances in low cost silicon manufacturing technology, it isbecoming apparent that in the future, electrical and computer engineers will most likelyimplement their digital designs, whether large or small, using programmable logic devices suchas CPLDs and FPGAs rather than discrete electronic components like integrated circuit chips,transistors, resistors, etc. This is becoming a reality in both small scale and medium scaleproduction volumes where quantities can run into thousands. On the other hand, even those whoare not focused on building careers based on digital circuit design will probably encounterelectronic systems built on such devices in their professional work. Therefore, it has becomenecessary to introduce related courses at undergraduate level along with a considerable numberof hands on laboratory sessions as well.This paper discusses the teaching and enhancements made to such courses in digital design toundergraduates majoring in Electrical Engineering Technology (EET). The author will elaboratethe attempts taken in promoting a certain level of excitement in students during the digitaldesign course. The paper also describes several considerations taken into account in theadaptation of Verilog Hardware Description Languages (HDL) and automation based digitaldesign flow to the EET curriculum several years ago. The demographics of the particularstudent population and their immediate careers suggested that most students would not pursuegraduate studies in computer engineering, nor would they seek employment related to designand manufacture of Integrated Circuit components. As a result, a much broader and deeperstudy of modern digital design methodologies has not been a necessity. Feedback from recentgraduates in industry has validated the adopted approaches while those pursuing graduatestudies appreciate the depth of the curriculum.At undergraduate level, digital designs described in HDL can start at two main differentabstraction levels: at schematic level, or at a higher register transfer level. Traditional designcourses are geared toward schematic based implementation flows which are tedious but lesschallenging for novice students than higher abstraction levels which demand comprehension ofadvanced design. However, incentives have been incorporated in to student work to describehardware designs at higher textual levels, and to use software packages for graphically viewingtheir low level implementations on computer. This circuit visualization was to provide a level ofexcitement among students to obtain variations in final implementations of their designs onprogrammable logic hardware boards.The paper will also present results from a student survey taken at the end of the course to gaugethe effectiveness of HDL based design flow, and how the graphical viewing of the final circuitsthat students designed at a higher textual level excited and incentivized students in theundergraduate EET program at this university.

Karunaratne, M. (2011, June), Does Logic Synthesis Visualization Excite EETs? Paper presented at 2011 ASEE Annual Conference & Exposition, Vancouver, BC. 10.18260/1-2--17792

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