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Parallel Simulation of Many-core Processors: Integration of Research and Education

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Conference

2012 ASEE Annual Conference & Exposition

Location

San Antonio, Texas

Publication Date

June 10, 2012

Start Date

June 10, 2012

End Date

June 13, 2012

ISSN

2153-5965

Conference Session

Integration of Research and Education in ECE

Tagged Division

Electrical and Computer

Page Count

11

Page Numbers

25.1024.1 - 25.1024.11

DOI

10.18260/1-2--21781

Permanent URL

https://peer.asee.org/21781

Download Count

175

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Paper Authors

biography

Tali Moreshet Swarthmore College

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Tali Moreshet is an Assistant Professor at the Department of Engineering at Swarthmore College. Her research interests are in computer architecture, energy-efficient multiprocessor, many-core, and embedded systems. Her research is funded by NSF. Moreshet earned a B.Sc in computer science from Technion, Israel Institute of Technology, and a M.Sc. and Ph.D. in computer engineering from Brown University.

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biography

Uzi Vishkin University of Maryland, College Park

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Uzi Vishkin has been professor of electrical and computer engineering and permanent of the University of Maryland Institute for Advanced Computer Studies (UMIACS) since 1988. He was affiliated with Tel Aviv University between 1984 and 1997, was Chair of CS there in 1987-8, and also worked for IBM, T.J. Watson and New York University. His research interests center around parallel algorithms and architectures. Facilitating a transition into ubiquitous parallel computing has been a strategic objective for computer science and engineering since its inception in the 1940s. A theory enthusiast, the overriding theme guiding his work was using theory to guide the rest of the field in addressing this strategic objective. Key components in his comprehensive plan include the very rich PRAM parallel algorithmic theory and a PRAM-on-Chip vision comprising the explicit multi-threaded (XMT) computer system framework he invented. The latter provides a powerful approach to multi-core architectures, and, in particular, the exponential increase in the number of cores in the roadmap of most vendors into the late 2010s. Recently, he has focused on the feedback loop between algorithms, their programming and implementation, and architecture, as well as their performance modeling with an eye towards softer aspects, such as their ease-of-programming, teachability, and learnability.

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Fuat Keceli Intel Corporation

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Abstract

Parallel Simulation of Many-core Processors: Integration of Research and EducationAbstractProviding undergraduate students with an opportunity to experience academic research has po-tential impact on their future career choice. More specifically, we believe that having a positiveresearch experience can motivate women and minority undergraduate engineering students to pur-sue an engineering career path, academic or otherwise. In this paper, we describe an on-going,multiple-year research project, led by undergraduate female students, which incorporates researchand education in computer science and engineering (CS&E). Our research project involves many-cores, which are becoming increasingly popular in general-purpose computing. While most researchers agree that this requires introduction of parallelism tomainstream CS&E practice, and hence education, parallel programming difficulties remain an ob-stacle that it yet to be overcome. The eXplicit Multi-Threading (XMT) framework provides ageneral-purpose many-core architecture for fine-grained parallel programs that scales to hundreds,or even thousands of lightweight cores. XMT aims at improving single task execution time throughparallelism, and has been supported by significant evidence on ease-of-programming and compet-itive performance. The XMT platform consists of a proof-of-concept 64-core FPGA and ASIC prototypes and ahighly configurable cycle-accurate simulator (XMTSim), capable of modeling a target 1024-coreXMT. Our work aims to parallelize XMTSim, with several objectives: (i) Long-term theoreticalobjective: Establish that XMT is an effective self simulating machine; namely simulating effi-ciently the XMTSim code by XMTSim itself. Recall that one of the elegant features of Turingmachines was their ability to provide self-simulations, and this was taken as evidence for theirgeneral-purposeness. (ii) Mid-term applicable objective: Speed up a many-core simulator by par-allelizing its most time-consuming components, beginning with the main simulation bottleneck,the Interconnection Network (ICN). (iii) Short-term training objective: Implementing a parallelapplication suitable for the XMT environment in the form of a parallel ICN. Our preliminary results for the short-term objective already show that parallelizing the ICNobtains simulation speedups of x54 compared to the best serial implementation on a 64-core XMT.We also explore alternative parallel implementations and demonstrate their potential advantage. While undergraduates realize that their work cannot achieve a high-impact research goal alone,we find that they appreciate being able to contribute towards a high-impact goal. Namely, toestablish, for the first time, that a parallel architecture (XMT, in this case) is general-purpose. Asexplained above, we plan to to do so by showing that XMT meets a classic understanding of whatgeneral-purpose computing is.

Moreshet, T., & Vishkin, U., & Keceli, F. (2012, June), Parallel Simulation of Many-core Processors: Integration of Research and Education Paper presented at 2012 ASEE Annual Conference & Exposition, San Antonio, Texas. 10.18260/1-2--21781

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