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Redesigning Computer Engineering Gateway Courses Using a Novel Remediation Hierarchy

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Conference

2016 ASEE Annual Conference & Exposition

Location

New Orleans, Louisiana

Publication Date

June 26, 2016

Start Date

June 26, 2016

End Date

August 28, 2016

ISBN

978-0-692-68565-5

ISSN

2153-5965

Conference Session

New Trends in ECE Education II

Tagged Division

Electrical and Computer

Page Count

23

DOI

10.18260/p.26063

Permanent URL

https://jee.org/26063

Download Count

231

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Paper Authors

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Ronald F. DeMara University of Central Florida Orcid 16x16 orcid.org/0000-0001-7859-9322

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Ronald F. DeMara is a Professor in the College of Engineering and Computer Science (CECS) with 23 years of university-level faculty experience in Electrical and Computer Engineering disciplines. He has completed 180+ technical and educational publications, 34 funded projects as PI/Co-I, and established two research laboratories. He serves as the Computer Engineering Program Coordinator, the founding Director of the Evaluation and Proficiency Center (EPC) in CECS, and is an iSTEM Fellow. He has developed 7 Computer Engineering courses which have been added to the UCF catalog as the sole developer, plus as the co-developer of 2 courses. He received the Joseph M. Bidenbach Outstanding Engineering Educator Award from IEEE in 2008.

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Navid Khoshavi University of Central Florida

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Navid Khoshavi is a Ph.D. student in Department of Electronic Engineering and Computer science at University of Central Florida. He engaged numerous students as a Graduate Teaching Assistant through providing visual aid to help student retention of abstract concepts, utilizing in-class activity to encourage students to put the concept into use and emphasizing critical concepts repeatedly to improve student long-term memory retention. He also received his M.S. from Amirkabir University of Technology (AUT) (Tehran Polytechnic), Iran, in 2012.

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Steven D. Pyle University of Central Florida

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Steven Pyle received B.Sc. and M.Sc. degrees in electrical engineering in 2013 and 2015 from the University of Central Florida. His first paper received the Best Design Paper Award at the 2015 Conference on Adaptive Hardware and Systems. He is continuing to pursue a Ph.D. degree in computer engineering at the University of Central Florida. His research interests include: Highly Parallel Computing Architectures, Adaptive Computer Architecture, Evolvable Hardware, Beyond CMOS Computing Architectures, particularly spintronics.

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John Edison University of Central Florida

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Computer Engineering, MS

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Richard Hartshorne University of Central Florida

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Richard Hartshorne is an Associate Professor and Coordinator for the Instructional Design & Technology program at the University of Central Florida (UCF). He earned his Ph.D. in Curriculum and Instruction with a focus on educational technology production and technology and teacher education from the University of Florida. Prior to his tenure at the UCF, Richard was an Assistant and Associate Professor of Instructional Systems Technology at the University of North Carolina at Charlotte for seven years and a physics instructor at Ed White High School in Jacksonville, FL for seven years. At the University of Central Florida, his teaching focuses on the integration of technology into the educational landscape, as well as instructional design and development. His research interests primarily involve the production and effective integration of instructional technology into the teaching and learning environment. The major areas of his research interest are rooted in technology and teacher education, the integration of emerging technology into the k-post-secondary curriculum, and online teaching and learning.

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Baiyun Chen University of Central Florida

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Dr. Baiyun Chen is an Instructional Designer at the Center for Distributed Learning at the University of Central Florida. She designs and delivers faculty professional development programs and teaches graduate courses on Instructional Systems Design. Her research interests focus on using instructional strategies in online and blended teaching and learning, professional development for teaching online, and application of emerging technologies in education. She has published 15 peer-reviewed journal articles and book chapters and delivered more than 50 presentations at international and local conferences and event and served as the Co-Managing Editor of the Teaching Online Pedagogical Repository.

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Michael Georgiopoulos University of Central Florida

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Michael Georgiopoulos received the Diploma in EE from the National Technical University in Athens, his MS degree and Ph.D. degree in EE from the University of Connecticut, Storrs, CT, in 1981, 1983 and
1986, respectively. He is currently a Professor in the Department of ECE at the University of Central Florida in Orlando, FL. From September 2011 to June 2012 he served as the Interim Assistant Vice President of Research at the Office of Research and Commercialization. From July 2012 to May 2013 he served as the Interim Dean of the College of Engineering and Computer Science. Since May 2013 he is serving as the dean of the College of Engineering and Computer Science at the University of Central Florida.

His research interests lie in the areas of Machine Learning and applications with special emphasis on neural network and neuro-evolutionary algorithms, and their applications. He has published more than 70 journal papers and more than 180 conference papers in a variety of conference and
journal venues. He has been an Associate Editor of the IEEE Transactions on Neural Networks from 2002 to 2006, and an Associate Editor of the Neural Networks journal from 2006 to 2012. He has served as the Technical Co-Chair of the IJCNN 2011.

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Ronald F. DeMara University of Central Florida Orcid 16x16 orcid.org/0000-0001-6864-7255

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Abstract

The TBA Department of Electrical and Computer Engineering has developed an Evaluation and Proficiency Infrastructure & Curricula (EPIC) and delivered it to approximately 700 students during multiple semesters in the required introductory courses: Engineering Analysis with C-Language, Computer Organization, Electrical Circuits, and Electrical Networks and Systems. The EPIC pedagogy:  engages students in a “flipped model” to master skills using both instructor-created and open resources,  enforces rigorous skill demonstration without aides using online assessments in a testing facility, and  enables scaffolding practices during tutoring between students and more knowledgeable GTAs. Student engagement is first increased by replacing homework assignments with Exemplar Vignettes already solved in detail on odd weeks, plus corresponding electronic assessments during even weeks. Second, utilizing a flipped classroom model, learners are assessed at times they prefer within a one-week Evaluation Window in a GTA-proctored Evaluation and Proficiency Center. Third, utilizing the Vygotskian concept of the Zone of Proximal Development (ZPD) and scaffolding, learners review their evaluation results with Content GTAs who are available to tutor due to the abridged homework and exam grading loads. Finally, learners requiring additional explanations visit their instructor to resolve concerns mediated as task/response flows within their individualized Learner Electronic Workspace. EPIC uses a layered remediation hierarchy to resolve two fundamental hurdles to utilizing electronic evaluation within STEM curricula. First, a taxonomy of online assessment instruments facilitates design problems beyond rote multiple choice. Thus, problems with partial credit which are isomorphic to pencil-and-paper based exams become deliverable electronically. Meanwhile handwritten image files are retained for strengthening the learner’s soft skills through one-on-one clarification with Content GTAs. Second, STEM learners require extensive guidance and student-specific coaching to hone their proficiency on subtle design aspects. A hierarchy of expertise facilitates these roles within a rapid feedback loop. A detailed financial cost model was developed which indicates that tutoring can be provided at no additional expense, by attaining a breakeven point between the grading hours avoided and the test proctoring hours required. This is shown to occur for a combined cohort of 1,150 students using EPIC per term. Thus, the EPIC pedagogy shifts instructor and GTA roles away from low-value repetitive tasks towards those having more significant impacts on learning outcomes. Students’ test scores and survey results indicate:  90% of respondents agreed that Exemplar Vignettes having detailed solutions along with a testing online assessment are more effective for learning than unguided homework assignments,  81% of respondents agreed that electronically-delivered quizzes and exams developed using the EPIC methodology were valid and appropriate assessment instruments, and  43% reduction in grades of D or F compared to a section of the same course, with the same instructor, using conventional delivery. In summary, EPIC improves learning quality by engaging students with scaffolding instruction targeted at the learners’ ZPD, while also systematically providing the instructor access to detailed formative statistics throughout the semester. It also mitigates increasing assignment preparation, instruction, and grading tasks of faculty and GTAs by refocusing instructor effort on curriculum tuning and renewal.

DeMara, R. F., & Khoshavi, N., & Pyle, S. D., & Edison, J., & Hartshorne, R., & Chen, B., & Georgiopoulos, M., & DeMara, R. F. (2016, June), Redesigning Computer Engineering Gateway Courses Using a Novel Remediation Hierarchy Paper presented at 2016 ASEE Annual Conference & Exposition, New Orleans, Louisiana. 10.18260/p.26063

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