DeMara, R. F., & Khoshavi, N., & Pyle, S. D., & Edison, J., & Hartshorne, R., & Chen, B., & Georgiopoulos, M., & DeMara, R. F. (2016, June), Redesigning Computer Engineering Gateway Courses  Using a Novel Remediation Hierarchy  Paper presented at 2016 ASEE Annual Conference & Exposition, New Orleans, Louisiana. 10.18260/p.26063

\bibitem{asee_peer_26063}
  DeMara, R. F., \& Khoshavi, N., \& Pyle, S. D., \& Edison, J., \& Hartshorne, R., \& Chen, B., \& Georgiopoulos, M., \& DeMara, R. F. (2016, June), \emph{Redesigning Computer Engineering Gateway Courses  Using a Novel Remediation Hierarchy}
  Paper presented at 2016 ASEE Annual Conference \& Exposition, New Orleans, Louisiana.
  10.18260/p.26063

Ronald F. DeMara, Navid Khoshavi, Steven D. Pyle, John Edison, Richard Hartshorne, Baiyun Chen, Michael Georgiopoulos, and Ronald F. DeMara.  "Redesigning Computer Engineering Gateway Courses  Using a Novel Remediation Hierarchy".  2016 ASEE Annual Conference & Exposition, New Orleans, Louisiana, 2016, June.  ASEE Conferences, 2016.  https://peer.asee.org/26063 Internet.  10 Oct, 2024

\bibitem{asee_peer_26063}
  Ronald F. DeMara, Navid Khoshavi, Steven D. Pyle, John Edison, Richard Hartshorne, Baiyun Chen, Michael Georgiopoulos, and Ronald F. DeMara.
  "Redesigning Computer Engineering Gateway Courses  Using a Novel Remediation Hierarchy".
  \emph{2016 ASEE Annual Conference \& Exposition, New Orleans, Louisiana, 2016, June}.
  ASEE Conferences, 2016.
  https://peer.asee.org/26063 Internet.  10 Oct, 2024

@INPROCEEDINGS{asee_peer_26063
author = "Ronald F. DeMara, Navid Khoshavi, Steven D. Pyle, John Edison, Richard Hartshorne, Baiyun Chen, Michael Georgiopoulos, and Ronald F. DeMara"
title = "Redesigning Computer Engineering Gateway Courses  Using a Novel Remediation Hierarchy"
booktitle = "2016 ASEE Annual Conference \& Exposition"
year = "2016"
month = "June"
address = "New Orleans, Louisiana"
publisher = "ASEE Conferences"
note = {https://peer.asee.org/26063}
number = {10.18260/p.26063}
}

TY  - CPAPER
AB  - The TBA Department of Electrical and Computer Engineering has developed an Evaluation and Proficiency Infrastructure & Curricula (EPIC) and delivered it to approximately 700 students during multiple semesters in the required introductory courses: Engineering Analysis with C-Language, Computer Organization, Electrical Circuits, and Electrical Networks and Systems.  The EPIC pedagogy: 
	engages students in a “flipped model” to master skills using both instructor-created and open resources,
	enforces rigorous skill demonstration without aides using online assessments in a testing facility, and
	enables scaffolding practices during tutoring between students and more knowledgeable GTAs.
Student engagement is first increased by replacing homework assignments with Exemplar Vignettes already solved in detail on odd weeks, plus corresponding electronic assessments during even weeks. Second, utilizing a flipped classroom model, learners are assessed at times they prefer within a one-week Evaluation Window in a GTA-proctored Evaluation and Proficiency Center.  Third, utilizing the Vygotskian concept of the Zone of Proximal Development (ZPD) and scaffolding, learners review their evaluation results with Content GTAs who are available to tutor due to the abridged homework and exam grading loads.  Finally, learners requiring additional explanations visit their instructor to resolve concerns mediated as task/response flows within their individualized Learner Electronic Workspace.
EPIC uses a layered remediation hierarchy to resolve two fundamental hurdles to utilizing electronic evaluation within STEM curricula.  First, a taxonomy of online assessment instruments facilitates design problems beyond rote multiple choice. Thus, problems with partial credit which are isomorphic to pencil-and-paper based exams become deliverable electronically. Meanwhile handwritten image files are retained for strengthening the learner’s soft skills through one-on-one clarification with Content GTAs.  Second, STEM learners require extensive guidance and student-specific coaching to hone their proficiency on subtle design aspects.  A hierarchy of expertise facilitates these roles within a rapid feedback loop. A detailed financial cost model was developed which indicates that tutoring can be provided at no additional expense, by attaining a breakeven point between the grading hours avoided and the test proctoring hours required.  This is shown to occur for a combined cohort of 1,150 students using EPIC per term. Thus, the EPIC pedagogy shifts instructor and GTA roles away from low-value repetitive tasks towards those having more significant impacts on learning outcomes.
Students’ test scores and survey results indicate:
	90% of respondents agreed that Exemplar Vignettes having detailed solutions along with a testing online assessment are more effective for learning than unguided homework assignments,
	81% of respondents agreed that electronically-delivered quizzes and exams developed using the EPIC methodology were valid and appropriate assessment instruments, and 
	43% reduction in grades of D or F compared to a section of the same course, with the same instructor, using conventional delivery.
In summary, EPIC improves learning quality by engaging students with scaffolding instruction targeted at the learners’ ZPD, while also systematically providing the instructor access to detailed formative statistics throughout the semester. It also mitigates increasing assignment preparation, instruction, and grading tasks of faculty and GTAs by refocusing instructor effort on curriculum tuning and renewal.

AU  - Ronald F. DeMara
AU  - Navid Khoshavi
AU  - Steven D. Pyle
AU  - John Edison
AU  - Richard Hartshorne
AU  - Baiyun Chen
AU  - Michael Georgiopoulos
AU  - Ronald F. DeMara
CY  - New Orleans, Louisiana
DA  - 2016/06/26
PB  - ASEE Conferences
TI  - Redesigning Computer Engineering Gateway Courses  Using a Novel Remediation Hierarchy
UR  - https://peer.asee.org/26063
DO  - 10.18260/p.26063
ER  -