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Using Genetic Algorithms In The Global Wiring Of Integrated Circuits

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Conference

2000 Annual Conference

Location

St. Louis, Missouri

Publication Date

June 18, 2000

Start Date

June 18, 2000

End Date

June 21, 2000

ISSN

2153-5965

Page Count

8

Page Numbers

5.693.1 - 5.693.8

Permanent URL

https://peer.asee.org/8811

Download Count

13

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Paper Authors

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Edgar N. Reyes

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Carl Steidley

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Mario Garcia

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Abstract
NOTE: The first page of text has been automatically extracted and included below in lieu of an abstract

Session 3520

Using Genetic Algorithms in the Global Wiring of Integrated Circuits

Edgar N. Reyes, Mario Garcia, and Carl W. Steidley Southeastern Louisiana University / Texas A&M University - Corpus Christi

Abstract Global wiring of integrated circuits is an engineering application using combinatorial opti- mization. In this paper, we interpret the problem of how to best wire an integrated circuit as a combinatorial optimization problem. We employ a genetic algorithm, which is a search tech- nique, to

Reyes, E. N., & Steidley, C., & Garcia, M. (2000, June), Using Genetic Algorithms In The Global Wiring Of Integrated Circuits Paper presented at 2000 Annual Conference, St. Louis, Missouri. https://peer.asee.org/8811

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