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5 Step Design Methodology For A General Purpose Cpu Using Standard Cplds/Fpgas

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Conference

2005 Annual Conference

Location

Portland, Oregon

Publication Date

June 12, 2005

Start Date

June 12, 2005

End Date

June 15, 2005

ISSN

2153-5965

Conference Session

Electrical & Computer Engineering Poster Session

Page Count

16

Page Numbers

10.8.1 - 10.8.16

Permanent URL

https://peer.asee.org/15391

Download Count

89

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Paper Authors

author page

Michael Anderton

author page

Karim Salman

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Abstract
NOTE: The first page of text has been automatically extracted and included below in lieu of an abstract

5-STEP DESIGN METHODOLOGY FOR A GENERAL PURPOSE CPU USING STANDARD CPLDs/FPGAs

Karim Salman, Michael B. Anderton

Middle Tennessee State University

Abstract

We present a novel hardware Central Processing Unit (CPU) design methodology based on a 5-step approach. The method starts with a definition of the target CPU internal components and data and address size. The method is applicable to a higher level of abstraction and complexity. However, for ease of illustration a basic CPU with a minimum size instruction set is selected. The instruction set complies with the instruction set completeness criteria. The instruction format is likewise chosen to be simple and illustrates the way our methodology is implemented. The CPU is implemented on an Altera FPGA/CPLD Flex10K device using schematic approach with the Altera MAX+Plus II software CAD. The design was simulated and tested using Altera UP2 board.

Introduction

CPU design for engineering/engineering technology students varied widely in objectives and approach1-7. For a long time, block diagrams of simple CPUs have been used in beginning computer courses, mainly to allow students to visualize how a CPU functions. To meet this need, many textbook authors1,6,7 have devised simple CPUs at the block diagram level to illustrate how instructions are executed and data are manipulated. Obviously, omitting many of the circuit details allows an overall understanding that is usually sufficient for students with little or no experience with digital circuits. However, students in accredited Electronics and Computer Engineering and Engineering Technology programs, have a more thorough background in digital circuit design. They are able to understand how instructions are decoded, what control signals are required for datapath operation, and how those control signals are generated. By examining this extra level of detail, students can better tie the new material to principles they have already learned. The low end approach is mainly descriptive of either a hypothetical ad hoc designs that remain to be implemented and tested4,6,8, or description of operation and design criteria of available well established designs10. On the high end, the approach usually departs and concentrates on describing complex architectures. This paper describes an architecture that is amenable to hardware implementation. A 5-step design methodology is presented. Although the paper adopts an already described architecture6,

“Proceedings of the 2005 American Society for Engineering Education Annual Conference & Exposition Copyright 2005, American Society for Engineering Education”

Anderton, M., & Salman, K. (2005, June), 5 Step Design Methodology For A General Purpose Cpu Using Standard Cplds/Fpgas Paper presented at 2005 Annual Conference, Portland, Oregon. https://peer.asee.org/15391

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