Conference Session

Engineering Education Research - Focus on Engineering Design

Collection

2017 FYEE Conference

Authors

Akhan Almagambetov, Embry-Riddle Aeronautical University, Prescott; John M. Pavlina, Embry-Riddle Aeronautical University, Prescott

Tagged Topics

FYEE Division - Paper Submission

RUBRIC and one minor error: stopped instead of triggered, AC (15 pts) Implement a logic circuit in VHDL and simulate all possibilities. 8 instead of DC biased Ind. Pts. Description Shows the full waveform in analog triggered with 0 Nothing provided E 10 correct values for period and voltage 2 Can write VHDL by hand U 3 Can open a program to write VHDL TABLE III 4 Can open