Asee peer logo

A Hierarchical Project-Based Introduction to Digital Logic Design Course

Download Paper |

Conference

2014 ASEE Annual Conference & Exposition

Location

Indianapolis, Indiana

Publication Date

June 15, 2014

Start Date

June 15, 2014

End Date

June 18, 2014

ISSN

2153-5965

Conference Session

Innovations in Computer Engineering Courses

Tagged Division

Electrical and Computer

Page Count

12

Page Numbers

24.54.1 - 24.54.12

Permanent URL

https://peer.asee.org/19946

Download Count

121

Request a correction

Paper Authors

biography

Bill D Carroll P.E. University of Texas, Arlington

visit author page

Bill Carroll is Professor of Computer Science and Engineering at The University of Texas at Arlington (UTA). He has been a UTA faculty member since 1981 and has held faculty positions at Auburn University and visiting appointments at the University of California-Berkeley and the University of Washington. He has held engineering positions at Texas Instruments and General Dynamics. Carroll received B.S., M.S., and Ph.D. degrees in electrical engineering from the University of Texas at Austin. He is a Fellow of the Institute for Electrical and Electronics Engineers (IEEE) and a licensed professional engineer in Texas and Alabama.

visit author page

biography

Shawn N Gieser University Of Texas At Arlington

visit author page

Shawn N. Gieser
PhD Student in Computer Science and part of the Heracleia Human-Centered Computing Laboratory in the Department of Computer Science and Engineering at The University of Texas at Arlington. Also, Graduate Teaching Assistant and Lab Instructor for Digital Logic.

visit author page

biography

David Levine University of Texas, Arlington

visit author page

David Levine teaches at the University of Texas at Arlington in Computer Science and Engineering. He teaches computer architecture, computer organization, cloud computing and operating systems, in the last course he enjoys using his textbook "Operating Systems a Spiral Approach" (McGraw-Hill), which he co-authored with Ramez Elmasri and Gil Carrick.

visit author page

Download Paper |

Abstract

A Hierarchical Project-Based Introduction to Digital Logic Design CourseCourses in digital logic design are required by virtually all electrical engineering and computerengineering programs and by many computer science programs. Credit hour reduction mandatesoften constrain coverage to a single required course. Typically, logic design courses coverfundamentals in lectures with applications and technology being covered in a laboratory setting.Also, these courses are well suited to address ABET student outcome requirements. However,coordinating the lectures with the laboratories can be challenging, and students often miss theconnection between fundamentals and the applications. Our introduction to digital logic coursehas been updated and restructured over the past two years to address these and other issues.This paper covers details of the restructured course and discusses lessons learned. Assessment isongoing and will be presented in the paper and conference presentation. For the past severalyears, the course has addressed ABET/EAC student outcomes (a), (c), and (k) with keyassignments and a design project at the end of the course. The project was necessarily limited inscope due to time constraints, student preparation, and the absence of lab resources to implementthe project. Students were required to design and simulate their project but not to implementand test it.The restructured course features a project that runs throughout the semester and culminates withimplementation and testing on a field-programmable gate array (FPGA). A hierarchical designapproach is used so that the results of weekly or biweekly lab exercises can be integrated for thefinal design. The project being incorporated in the course is the design of a basic four-bitcomputer processing unit. Students design and implement a four-function ALU fromcombinational logic during the first third of the course. The middle-third of the course focuseson the design and implementation of the various registers and counters needed in the processor.The final third covers design of the control unit and integration of the previously designedcomponents. All design work is captured and simulated using the Altera Quartus II designsoftware and then implement using an Altera Cyclone II FPGA on an Altera DE-1 developmentboard. Some components are also implemented using basic integrated circuits on solder-lessbreadboards. This gives students hands-on experience constructing, testing, and debuggingcircuits that cannot be gained from FPGA implementation. A written project report is required atthe end of the semester.Laboratory assignments are introduced during lectures. This provides better linkage between thefundamentals being covered in the lectures and the applications and hands-on laboratoryexperiences. This approach also allows for an earlier inclusion of interesting and meaningfullaboratory exercises.In summary, the restructured introduction to digital logic course incorporates a semester-longdesign and implementation project that follows a hierarchical design approach. This is enabledby the use of powerful design capture and simulation software during design and easy to useFPGA technology for implementation and testing. Emphasis on fundamentals is maintained byclose linkage of lecture and hands-on laboratory exercises.

Carroll, B. D., & Gieser, S. N., & Levine, D. (2014, June), A Hierarchical Project-Based Introduction to Digital Logic Design Course Paper presented at 2014 ASEE Annual Conference & Exposition, Indianapolis, Indiana. https://peer.asee.org/19946

ASEE holds the copyright on this document. It may be read by the public free of charge. Authors may archive their work on personal websites or in institutional repositories with the following citation: © 2014 American Society for Engineering Education. Other scholars may excerpt or quote from these materials with the same citation. When excerpting or quoting from Conference Proceedings, authors should, in addition to noting the ASEE copyright, list all the original authors and their institutions and name the host city of the conference. - Last updated April 1, 2015