Asee peer logo

A Novel Technique for Low-Power Electronic System Design

Download Paper |


2016 ASEE Annual Conference & Exposition


New Orleans, Louisiana

Publication Date

June 26, 2016

Start Date

June 26, 2016

End Date

August 28, 2016





Conference Session

Electrical and Computer Division Poster Session

Tagged Division

Electrical and Computer

Page Count




Permanent URL

Download Count


Request a correction

Paper Authors


Evelyn Sowells-Boone North Carolina A&T State University Orcid 16x16

visit author page

Dr. Evelyn R. Sowells is an assistant professor in the Computer Systems Technology department at North Carolina A&T State University’s School of Technology. Prior to joining the School of Technology faculty, she held position at U.S. Department of Energy, N.C. A&T’s Division of Research and College of Engineering. Dr. Sowells earned a Ph.D. in Electrical Engineering from North Carolina A&T State University’s College of Engineering. She also holds a M.S. and B.S in Computer Science with a concentration in software engineering from the same university. Her primary research interests are in the areas of low-power high performance digital systems design, asynchronous design, self-timed digital system design and STEM education. As a result of her work, she has numerous peer reviewed journal and conference publications. She recently authored a book entitled “Low Power Self-Timed Size Optimization for an Input Data Distribution,” which explores innovative techniques to reduce power consumption for portable electronic devices. She was recently awarded the 2016 Chair’s award for Rookie Researcher of the year in the Computer System Technology department. Dr. Sowells is the lead investigator of the Females in Technology (FiT) summer boot camp grant project for academically gifted low income rising senior and junior high girls for recruitment into the technology degree areas. She is also the co-PI of the Aggie STEM Minority Male Maker grant project focused on early exposure to technology to stimulate interest in technology of middle school minority males. Evelyn is not only outstanding in teaching and research, but also in service. She recently received the 2013 Chair’s Award for Outstanding Service in the Department of Computer System Technology and is a member of Upsilon Phi Epsilon, Computer Science Honor Society, American Society of Engineering Education’s Electronic Technology and Women in Engineering Divisions, and American Association of University Women.

visit author page


Cameron Seay North Carolina A&T State University

visit author page

Cameron Seay is an Assistant Professor in the Department of Computer Systems Technology at North Carolina A&T State University. He holds a doctorate in educational psychology and advanced degrees in business, computer information systems and economics.

visit author page


Dewayne Randolph Brown North Carolina A&T State University

visit author page

Dr. DeWayne Brown received his Ph.D. in Electrical Engineering from Virginia Polytechnic Institute and State University, 1997. He received his Master’s Degree in Electrical Engineering, North Carolina A & T State University in 1992. He received his Bachelor’s Degree in Electrical and Computer Engineering from the University of South Carolina in 1990. Dr. Brown’s research interests are wireless communications, navigation, and electrical energy. Dr. Brown was employed at North Carolina Agricultural and Technical University since 1997.

visit author page

Download Paper |


The central focus of digital system design engineers over the past two decades has been on the trade-offs between the power/energy and performance of the circuits implemented in current and emerging nanometer-scale VLSI technologies. A number of techniques have been developed to address this design challenge; one approach is based on a class of asynchronous pipelined digital circuit structures that are called self-timed. The dynamic power/energy dissipation is reduced in this realization, relative to synchronous implementations, because all clocks are generated locally and circuit timing and control is event driven. The performance of these circuits can exceed synchronous realization because it is based on the average intrinsic timing of the circuit instead of its worst case timing that is used to set the clock frequency in synchronous systems. The circuit design process used to determine the device sizing in self-timed circuits/systems is typically the same as that used for synchronous realizations. The input distribution is not considered in this process. A novel self-timed circuit design technique that out performs previously proposed approaches is presented in this paper. The input data distribution is used in the proposed technique to optimize the circuit performance for the respective input data set probability distribution.

Sowells-Boone, E., & Seay, C., & Brown, D. R. (2016, June), A Novel Technique for Low-Power Electronic System Design Paper presented at 2016 ASEE Annual Conference & Exposition, New Orleans, Louisiana. 10.18260/p.26385

ASEE holds the copyright on this document. It may be read by the public free of charge. Authors may archive their work on personal websites or in institutional repositories with the following citation: © 2016 American Society for Engineering Education. Other scholars may excerpt or quote from these materials with the same citation. When excerpting or quoting from Conference Proceedings, authors should, in addition to noting the ASEE copyright, list all the original authors and their institutions and name the host city of the conference. - Last updated April 1, 2015