New Orleans, Louisiana
June 26, 2016
June 26, 2016
August 28, 2016
Electrical and Computer
The central focus of digital system design engineers over the past two decades has been on the trade-offs between the power/energy and performance of the circuits implemented in current and emerging nanometer-scale VLSI technologies. A number of techniques have been developed to address this design challenge; one approach is based on a class of asynchronous pipelined digital circuit structures that are called self-timed. The dynamic power/energy dissipation is reduced in this realization, relative to synchronous implementations, because all clocks are generated locally and circuit timing and control is event driven. The performance of these circuits can exceed synchronous realization because it is based on the average intrinsic timing of the circuit instead of its worst case timing that is used to set the clock frequency in synchronous systems. The circuit design process used to determine the device sizing in self-timed circuits/systems is typically the same as that used for synchronous realizations. The input distribution is not considered in this process. A novel self-timed circuit design technique that out performs previously proposed approaches is presented in this paper. The input data distribution is used in the proposed technique to optimize the circuit performance for the respective input data set probability distribution.
Sowells, E., & Seay, C., & Brown, D. R. (2016, June), A Novel Technique for Low-Power Electronic System Design Paper presented at 2016 ASEE Annual Conference & Exposition, New Orleans, Louisiana. 10.18260/p.26385
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