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An Analysis Of Clock Jitter On An Analog To Digital Converter Using The Signal Processing Worksystem (Spw) Environment

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Conference

1997 Annual Conference

Location

Milwaukee, Wisconsin

Publication Date

June 15, 1997

Start Date

June 15, 1997

End Date

June 18, 1997

ISSN

2153-5965

Page Count

5

Page Numbers

2.63.1 - 2.63.5

Permanent URL

https://peer.asee.org/6419

Download Count

128

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Paper Authors

author page

Shonda L. Williams

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Abstract
NOTE: The first page of text has been automatically extracted and included below in lieu of an abstract

Session 1220

An Analysis of Clock-Jitter on an Analog-to-Digital Converter Using the Signal Processing Worksystem (SPW) Environment

Shonda L. Williams Student, Department of Electrical Engineering Florida A&M University and Florida State University

ABSTRACT- A sound fundamental understanding of electronic circuits and devices can be used as a basis to formulate an understanding of ADC computer interface devices. However, secondary effects such as offset, drift, clock-jitter, etc. may represent critical characteristics that must be understood and dealt with. The author presents an analysis of an Analog-to-Digital Converter (ADC) simulation that includes the jitter present in real ADC clock-circuitry. The paper exemplifies the in-depth analysis needed to understand some of the secondary nonlinear physical properties of electronic devices as they relate to ADC devices.

Introduction

Digital Signal Processing (DSP) is rapidly becoming a key technology of the future as the data generated by the information age expands exponentially. This data must be acquired as well as processed. The Analog-to-Digital Converter (ADC) is a key computer interface component for acquiring data. Although the fundamental operations of these devices are relatively simple; subtle and secondary effects, such as offset, drift, clock-jitter, etc., can become critical factors in integrated applications. These effects must be understood and accounted for. For one example, the author presents an analysis of an ADC simulation that includes the jitter present in real ADC clock-circuitry.

The analysis will feature a mathematical approach needed to determine an effective method for simulating the jitter that is present in a real ADC clock. The Signal Processing Worksystem (SPW) will be used to implement a block diagram-based ADC simulation [1]. The basic approach is to use one of the perfect ADC models within SPW and then add the clock-jitter component to the simulation. An analysis of an ADC model will be conducted to determine the effect of clock-jitter on a signal as it passes through the ADC.

As implied, when implementing ADC interface devices, it is important that secondary effects, such as clock-jitter, produce negligible effects on an integrated system so that the system desired operational characteristics are achieved. Consequently, studying these secondary effects within a single component through computer simulations, will prove beneficial to understanding the performance of interface devices when they are integrated into complete systems or system components. Appreciation is expressed to the Hughes Space and Communication Division for its support in this work.

Williams, S. L. (1997, June), An Analysis Of Clock Jitter On An Analog To Digital Converter Using The Signal Processing Worksystem (Spw) Environment Paper presented at 1997 Annual Conference, Milwaukee, Wisconsin. https://peer.asee.org/6419

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