Rajaei, H. (2020, June), An Empirical Study for Multilevel Cache Associativity  Paper presented at 2020 ASEE Virtual Annual Conference Content Access, Virtual On line . 10.18260/1-2--34115

\bibitem{asee_peer_34115}
  Rajaei, H. (2020, June), \emph{An Empirical Study for Multilevel Cache Associativity}
  Paper presented at 2020 ASEE Virtual Annual Conference Content Access, Virtual On line .
  10.18260/1-2--34115

Hassan Rajaei.  "An Empirical Study for Multilevel Cache Associativity".  2020 ASEE Virtual Annual Conference Content Access, Virtual On line , 2020, June.  ASEE Conferences, 2020.  https://peer.asee.org/34115 Internet.  11 Jan, 2025

\bibitem{asee_peer_34115}
  Hassan Rajaei.
  "An Empirical Study for Multilevel Cache Associativity".
  \emph{2020 ASEE Virtual Annual Conference Content Access, Virtual On line , 2020, June}.
  ASEE Conferences, 2020.
  https://peer.asee.org/34115 Internet.  11 Jan, 2025

@INPROCEEDINGS{asee_peer_34115
author = "Hassan Rajaei"
title = "An Empirical Study for Multilevel Cache Associativity"
booktitle = "2020 ASEE Virtual Annual Conference Content Access"
year = "2020"
month = "June"
address = "Virtual On line "
publisher = "ASEE Conferences"
note = {https://peer.asee.org/34115}
number = {10.18260/1-2--34115}
}

TY  - CPAPER
AB  - An Empirical Study for Multi-Level Cache Associativity  
 
Abstract
 
Most CPUs architecture use multi-level caches with different associativity. A cache plays an essential role by providing fast access to the instructions and data to improve the overall performance of the system. To demonstrate the complexity of the issue in an advanced computer architecture course, we used an empirical simulation study to focus on performance of multi-level caches and their associativity. This paper presents the result of such study. Designing and predicting caches behavior has been subject of numerous simulation studies. Cache simulation tools provide support for diverse configurations of the system with multiple scenarios to ensure the system could perform at peak level. In this study, we explore multi-level caches and their performance when changing various associativity and block size. 

We surveyed several simulation studies specialized for cache design and processor performance. We chose two tools, CACTI 5.3 and SimpleScalar 3.0, to empirically study and analyze numerous configurations. We cross-examined the base model by adding cache associativity to check performance implications of each configuration. CACTI helped to compare several scenarios based on access time, cycle time, and other factors. SimpleScalar helped to better analyze the results based on factors such as total number of instructions executed and hit- or miss-rates. In addition, we combined the access time from CACTI the one from SimpleScalar to get total number of Access per second. Our results were scrutinized against others and found that in most cases they were similar or slightly improved for multilevel cache associativity.


AU  - Hassan Rajaei
CY  - Virtual On line 
DA  - 2020/06/22
PB  - ASEE Conferences
TI  - An Empirical Study for Multilevel Cache Associativity
UR  - https://peer.asee.org/34115
DO  - 10.18260/1-2--34115
ER  -