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An Empirical Study for Multilevel Cache Associativity

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Conference

2020 ASEE Virtual Annual Conference Content Access

Location

Virtual On line

Publication Date

June 22, 2020

Start Date

June 22, 2020

End Date

June 26, 2021

Conference Session

Computing and Information Technology Division Technical Session 7

Tagged Division

Computing and Information Technology

Page Count

13

DOI

10.18260/1-2--34115

Permanent URL

https://peer.asee.org/34115

Download Count

644

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Paper Authors

biography

Hassan Rajaei Bowling Green State University

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Hassan Rajaei is a professor of computer science at Bowling Green State University, Ohio. His research interests include cloud computing, High Performance Computing (HPC), distributed simulation, parallel and distributed processing, communication networks, wireless communications, and IoT. Rajaei received his Ph.D. from Royal Institute of Technology, KTH, Stockholm, Sweden, and he holds a M.S.E.E. from the University of Utah, and a BS from University of Tehran.

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Abstract

An Empirical Study for Multi-Level Cache Associativity Abstract Most CPUs architecture use multi-level caches with different associativity. A cache plays an essential role by providing fast access to the instructions and data to improve the overall performance of the system. To demonstrate the complexity of the issue in an advanced computer architecture course, we used an empirical simulation study to focus on performance of multi-level caches and their associativity. This paper presents the result of such study. Designing and predicting caches behavior has been subject of numerous simulation studies. Cache simulation tools provide support for diverse configurations of the system with multiple scenarios to ensure the system could perform at peak level. In this study, we explore multi-level caches and their performance when changing various associativity and block size.

We surveyed several simulation studies specialized for cache design and processor performance. We chose two tools, CACTI 5.3 and SimpleScalar 3.0, to empirically study and analyze numerous configurations. We cross-examined the base model by adding cache associativity to check performance implications of each configuration. CACTI helped to compare several scenarios based on access time, cycle time, and other factors. SimpleScalar helped to better analyze the results based on factors such as total number of instructions executed and hit- or miss-rates. In addition, we combined the access time from CACTI the one from SimpleScalar to get total number of Access per second. Our results were scrutinized against others and found that in most cases they were similar or slightly improved for multilevel cache associativity.

Rajaei, H. (2020, June), An Empirical Study for Multilevel Cache Associativity Paper presented at 2020 ASEE Virtual Annual Conference Content Access, Virtual On line . 10.18260/1-2--34115

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