Asee peer logo

An Engineering Application Of The Simulated Annealing Algorithm

Download Paper |

Conference

1999 Annual Conference

Location

Charlotte, North Carolina

Publication Date

June 20, 1999

Start Date

June 20, 1999

End Date

June 23, 1999

ISSN

2153-5965

Page Count

8

Page Numbers

4.66.1 - 4.66.8

Permanent URL

https://peer.asee.org/7628

Download Count

17

Request a correction

Paper Authors

author page

Edgar N. Reyes

author page

Carl W. Steidley

Download Paper |

Abstract
NOTE: The first page of text has been automatically extracted and included below in lieu of an abstract

Session 3420

An Engineering Application of the Simulated Annealing Algorithm Edgar N. Reyes, Carl W. Steidley Southeastern Louisiana University / Texas A&M University - Corpus Christi

1 Introduction Global wiring of integrated circuits is an engineering application using both combinatorial optimization and statistical physics. In this paper, we interpret the problem of how to best wire an integrated circuit as a combinatorial optimization problem. We employ a random search technique, namely, the simulated annealing algorithm, to

Reyes, E. N., & Steidley, C. W. (1999, June), An Engineering Application Of The Simulated Annealing Algorithm Paper presented at 1999 Annual Conference, Charlotte, North Carolina. https://peer.asee.org/7628

ASEE holds the copyright on this document. It may be read by the public free of charge. Authors may archive their work on personal websites or in institutional repositories with the following citation: © 1999 American Society for Engineering Education. Other scholars may excerpt or quote from these materials with the same citation. When excerpting or quoting from Conference Proceedings, authors should, in addition to noting the ASEE copyright, list all the original authors and their institutions and name the host city of the conference. - Last updated April 1, 2015