Hayne, R. J. (2011, June), An Instructional Processor Design Using VHDL and an FPGA  Paper presented at 2011 ASEE Annual Conference & Exposition, Vancouver, BC. 10.18260/1-2--17463

\bibitem{asee_peer_17463}
  Hayne, R. J. (2011, June), \emph{An Instructional Processor Design Using VHDL and an FPGA}
  Paper presented at 2011 ASEE Annual Conference \& Exposition, Vancouver, BC.
  10.18260/1-2--17463

Ronald J. Hayne.  "An Instructional Processor Design Using VHDL and an FPGA".  2011 ASEE Annual Conference & Exposition, Vancouver, BC, 2011, June.  ASEE Conferences, 2011.  https://peer.asee.org/17463 Internet.  04 Dec, 2024

\bibitem{asee_peer_17463}
  Ronald J. Hayne.
  "An Instructional Processor Design Using VHDL and an FPGA".
  \emph{2011 ASEE Annual Conference \& Exposition, Vancouver, BC, 2011, June}.
  ASEE Conferences, 2011.
  https://peer.asee.org/17463 Internet.  04 Dec, 2024

@INPROCEEDINGS{asee_peer_17463
author = "Ronald J. Hayne"
title = "An Instructional Processor Design Using VHDL and an FPGA"
booktitle = "2011 ASEE Annual Conference \& Exposition"
year = "2011"
month = "June"
address = "Vancouver, BC"
publisher = "ASEE Conferences"
note = {https://peer.asee.org/17463}
number = {10.18260/1-2--17463}
}

TY  - CPAPER
AB  -            An Instructional Processor Design using VHDL and an FPGAAbstractMost modern commercial microprocessors are too complex to be used as an introductoryexample of processor design. Many digital design courses and texts use hardware descriptionlanguage models of these processors, but they are often ad hoc and don't divide the architectureinto teachable subsets. What is needed is a basic processor with sufficient complexity toillustrate major design elements, that can be modified, programmed, and tested.An instructional processor has been developed for use as a design example in an AdvancedDigital Systems course. The architecture is separated into the data path and a sequentialcontroller. The data path contains the memory, registers, arithmetic logic unit, andinterconnecting busses. The controller implements the fetch, decode, and execute sequences fora small subset of instructions. The entire system is modeled in VHDL and can be simulated todemonstrate operation of the processor.The instruction set architecture of the example processor has been designed to illustrate multipleoperations and basic addressing modes. The initial subset includes opcodes for move, add, andbranch, with the capability to modify or supplement these instructions. Access to operandsinclude provisions for direct, indirect and immediate addressing modes. Test programs arewritten in assembly language and translated into machine code for loading into memory. Asimple example program adds two arrays of numbers and illustrates the fundamental concepts ofcounting, indexing, and looping.Design of the instructional processor is taught in sections covering the instruction setarchitecture, followed by implementation of the data path, and finally the fetch, decode andexecute sequences for the control unit. Each component is modeled in VHDL and functionallyverified using ModelSim. Student homework assignments then involve modification of theVHDL model to implement additional instructions. The upgraded processor is verified by thestudents via execution of their own test programs.As an extension of the processor design, a basic microcontroller is created by adding simplememory-mapped input and output. Along with a few additional instructions, the system isimplemented in hardware on a field programmable gate array (FPGA). Students have theopportunity to interact with programs running on the instructional processor via input switchesand output LEDs. Timing loops create the ability to produce various flashing and shiftingpatterns to demonstrate operation of the microcontroller system.Implementation of the instructional processor is now in its second iteration with an updatedcontroller design and the new microcontroller extension. Student feedback is very positive thatthe processor illustrates fundamental design concepts without unnecessary complexity. Resultsfrom homework submissions indicate that the students are able to successfully designmodifications to the processor and demonstrate their functionality via simulation. The projectcontinues to achieve its goal as a valuable instructional tool.
AU  - Ronald J. Hayne
CY  - Vancouver, BC
DA  - 2011/06/26
PB  - ASEE Conferences
TI  - An Instructional Processor Design Using VHDL and an FPGA
UR  - https://peer.asee.org/17463
DO  - 10.18260/1-2--17463
ER  -