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An Sdl (Simple Description Language) Analyzer

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Conference

2001 Annual Conference

Location

Albuquerque, New Mexico

Publication Date

June 24, 2001

Start Date

June 24, 2001

End Date

June 27, 2001

ISSN

2153-5965

Page Count

16

Page Numbers

6.188.1 - 6.188.16

Permanent URL

https://peer.asee.org/9764

Download Count

71

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Paper Authors

author page

Robert Borrmann

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Abstract
NOTE: The first page of text has been automatically extracted and included below in lieu of an abstract

A1420

An SDL (Simple Description Language) Analyzer Robert J. Borrmann, Ph.D. Professor of Electrical and Computer Engineering Manhattan College New York City

Abstract

Second-year students in Manhattan’s four-year Electrical Engineering and Computer Engineering programs are introduced to digital circuits in a one-semester 3-credit course ELEC-229. This course includes a laboratory component in which students design and breadboard simple circuits. While the course includes preliminary coverage of VHDL (Very High Speed Integrated Circuits Hardware Description Language), the author believes that an easier introductory language and analysis tool, designed to parallel the student's progress in learning digital concepts, can help them gain confidence and familiarity with the strengths and weaknesses of digital simulation.

The SDL Analyzer described in this paper uses the power of Visual Basic graphics to provide simple logic simulation capabilities for small circuits of the complexity typically found in introductory courses. It is designed as a tutorial aid for students in digital analysis and design courses, and is based on the author's experience teaching the material in the college classroom. Compared with standard VHDL simulators, SDL provides a simpler user interface and reduced capabilities. Students can operate it interactively on their own computers, and study circuit operations step-by-step at their own pace. They can stimulate the circuit interactively, and view the results of analysis, either in tabular form or on the schematic drawn by the analyzer. All results can be saved to disk or printed.

This paper describes the SDL language, the SDL analyzer, and includes comparisons of SDL with ABEL and with VHDL, and the author's experiences using SDL in the classroom.

I. Introduction.

It is an accepted principle that students' learning of engineering concepts can be aided by providing them with suitable computer simulation tools. In their first course in digital systems, engineering students are introduced to logic gates, binary and hexadecimal numbers, flipflops, registers, and memory. A number of general-engineering tools are available, such as MATLAB1 and MathCad2, but these require some programming by the user to simulate digital circuits. Some programs are tailored to digital simulation, at least in part. This list includes ABEL3, Electronics Workbench4, LogicWorks5, PSPICE6, VHDL7, and others. These packages vary in a number of respects, including power, cost, complexity, suitability for classroom use, and schematic capture. Those that rely

Proceedings of the 2001 American Society for Engineering Education Annual Conference & Exposition Copyright  2001, American Society for Engineering Education

Borrmann, R. (2001, June), An Sdl (Simple Description Language) Analyzer Paper presented at 2001 Annual Conference, Albuquerque, New Mexico. https://peer.asee.org/9764

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