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Animation Of Vlsi Cad Algorithms: A Case Study

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Conference

2002 Annual Conference

Location

Montreal, Canada

Publication Date

June 16, 2002

Start Date

June 16, 2002

End Date

June 19, 2002

ISSN

2153-5965

Conference Session

Computed Simulation and Animation

Page Count

9

Page Numbers

7.204.1 - 7.204.9

Permanent URL

https://peer.asee.org/10294

Download Count

81

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Paper Authors

author page

John Nestor

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Abstract
NOTE: The first page of text has been automatically extracted and included below in lieu of an abstract

Main Menu Session 2220

Animation of VLSI CAD Algorithms – A Case Study

John A. Nestor Department of Electrical and Computer Engineering Lafayette College

Abstract

The design of modern VLSI chips requires the extensive use of Computer-Aided Design (CAD) tools. Undergraduate VLSI Design courses typically teach the use of these tools to create designs, but provide little or no information about how the tools work, which makes it difficult to use them effectively. The goal of the CADAPPLETS project is to provide a set of Java animations which will aid students in visualizing the internal operation of these tools in terms of common problem formulations, classes of algorithms, and specific algorithms. This paper describes one set of animations that illustrates the operation of placement tools, which assign cells to physical locations in a layout. This and other animations are used in class presentations in Lafayette College’s undergraduate VLSI courses and are available at http://foghorn.cadlab.lafayette.edu/cadapplets/.

1. Introduction

Modern VLSI chips are being designed at seemingly ever-increasing levels of complexity. Current chip designs commonly contain tens of millions of transistors, and larger chips are on the horizon. The design of such complex chips would be impossible without a wide range of Computer-Aided Design (CAD) tools. These tools automate different parts of the design process, making it possible to complete a large design in a reasonable amount of time while managing an enormous amount of detail. Input Specification (HDL)

Logic Optimization Logic Synthesis Technology Mapping

Netlist

Placement Physical Design Routing

Complete Layout

Figure 1 – Simplified Design Flow for Semi-Custom Chips

Figure 1 shows a simplified diagram of CAD tools used in the design of semi-custom VLSI chips – a popular style in which a pre-designed library of standard cells is used to speed the design process. Input is in the form of a Hardware Description Language

Proceedings of the 2002 American Society for Engineering Education Annual Conference & Exposition Copyright © 2002, American Society for Engineering Education

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Nestor, J. (2002, June), Animation Of Vlsi Cad Algorithms: A Case Study Paper presented at 2002 Annual Conference, Montreal, Canada. https://peer.asee.org/10294

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