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Asynchronous Finite State Machine Design: A Lost Art?

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Conference

2006 Annual Conference & Exposition

Location

Chicago, Illinois

Publication Date

June 18, 2006

Start Date

June 18, 2006

End Date

June 21, 2006

ISSN

2153-5965

Conference Session

Embedded Computing

Tagged Division

Computers in Education

Page Count

8

Page Numbers

11.258.1 - 11.258.8

Permanent URL

https://peer.asee.org/379

Download Count

4552

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Paper Authors

biography

Christopher Carroll University of Minnesota-Duluth

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Christopher R. Carroll earned his academic degrees from Georgia Tech and from Caltech. He is Director of Undergraduate Engineering in the College of Science and Engineering at the University of Minnesota Duluth and serves in the department of Electrical and Computer Engineering. His interests include special-purpose digital systems, VLSI, and microprocessor applications, especially in educational environments.

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Abstract
NOTE: The first page of text has been automatically extracted and included below in lieu of an abstract

Asynchronous Finite State Machine Design: A Lost Art? Abstract

As taught in most introductory digital circuit classes, design of sequential digital circuits is limited to a very strict set of restrictions, usually called “synchronous” finite state machine design. In synchronous design, there is one special signal called the “clock” which controls the timing of all state transitions, and all clock inputs on all sequential components in the digital system (flip-flops or other more complex components) must connect directly to that one clock signal in the system, without exception. Furthermore, all variables in the system are restricted to change only on the clock transition that causes state changes in the sequential components of the system. There is good reason to impose these restrictions in an introductory class. Working under the “synchronous” umbrella protects the designer from many timing problems that can occur in systems if these restrictions are not followed. However, examples abound where synchronous restrictions must be violated. For example, when a manually controlled switch input enters an otherwise synchronous system, the manual switch variable can change value at times unrelated to the clock transition, violating synchronous restrictions and causing headaches.

In fact, synchronous design techniques, and other related design regimens, are special cases of the more general design approach called “asynchronous” finite state machine design. In asynchronous design, there is no special clock signal to cause state changes. Instead, the state machine reacts to changes on the input variables from the environment. Flip-flops, for example, actually are not elementary building blocks of digital circuits as is taught in introductory courses. Flip-flops themselves are designed as asynchronous circuits. The memory in sequential circuits arises from the feedback present in asynchronous design to implement states in the state machine operation. In asynchronous sequential circuit design, there are no artificial restrictions on circuit behavior. As a result, however, there are many more concerns that must be addressed by the designer in order to ensure correct circuit operation, so asynchronous design is usually omitted from discussion in introductory digital courses.

This paper addresses some issues related to asynchronous finite state machine design, and includes some important examples of specific asynchronous circuits that have central significance in digital design. Techniques are included here to incorporate asynchronous design into lab experiments for advanced digital design courses. Without an understanding of the issues presented here, digital designers must work in a design environment that unnecessarily limits what they can do.

Carroll, C. (2006, June), Asynchronous Finite State Machine Design: A Lost Art? Paper presented at 2006 Annual Conference & Exposition, Chicago, Illinois. https://peer.asee.org/379

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