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Automated Measurement Of Mos Capacitance And Determination Of Mos Process Parameters In The Micro Fabrication Laboratory

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Conference

1997 Annual Conference

Location

Milwaukee, Wisconsin

Publication Date

June 15, 1997

Start Date

June 15, 1997

End Date

June 18, 1997

ISSN

2153-5965

Page Count

10

Page Numbers

2.87.1 - 2.87.10

Permanent URL

https://peer.asee.org/6431

Download Count

1033

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Paper Authors

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Mustafa Guvench

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Abstract
NOTE: The first page of text has been automatically extracted and included below in lieu of an abstract

Session 2659

Automated Measurement of MOS Capacitance and Determination of MOS Process Parameters in The MicroFabrication Laboratory

Mustafa G. Guvench University of Southern Maine

Abstract

This paper describes, (1) how to inexpensively automate measurement of MOS diode C-V characteristics by employing standard test equipment available in a computer integrated electronics instructional laboratory, and (2) a technique that facilitates accurate extraction of MOS and structural parameters such as the threshold and flatband voltages, the gate oxide thickness, and the semiconductor doping concentration from the acquired data for the evaluation of an MOS device fabrication process in a microfabrication laboratory. Low cost, simplicity, and accuracy warrant adoption of both for instruction as well as research. The extraction technique is based on a nonlinear mapping of the C-V data which helps clearly demarcate the three modes of the MOS operation, accumulation, depletion, and inversion. It is also shown that the slope of the resulting curve yields an accurate measure of the semiconductor substrate doping. The technique and its accurate yielding of doping have been verified theoretically with MathCad simulations. The measurement setup and the extraction technique have been used to evaluate the MOS samples made in-house as part the microfabrication course taught at the University of Southern Maine.

1. Introduction

The Metal-Oxide-Semiconductor structure, universally referred as the “MOS”, beside forming the basis of the working of the MOS Field Effect Transistor (MOSFET) which is the backbone of our integrated circuits, lends itself as a diagnostic tool for determining the quality of the process used in the fabrication of an integrated circuit. Therefore, it constitutes an essential part of semiconductor wafer fabrication as well as semiconductor device physics and deserves emphasis as an instructional tool and fundamental background status in the microelectronics education, both undergraduate and graduate [3]. However, the equipment available for MOS capacitance testing is either too specialized and expensive, making it a “push-button” experience and unaffordable, or very crude and manual, making it too time consuming to use as an instructional tool in a class setting. Detailed discussions of the MOS physics, MOS capacitance theory and measurements can be found in the literature (Sze [5], Streetman [6] and Schroder [7]). Simply stated, the MOS structure, since it is a sandwich of conductor-insulator-semiconductor, constitutes a capacitor whose capacitance varies in response to the total voltage applied (please see Figure 1). This variation is due to the semiconductor which can be depleted of its majority

Guvench, M. (1997, June), Automated Measurement Of Mos Capacitance And Determination Of Mos Process Parameters In The Micro Fabrication Laboratory Paper presented at 1997 Annual Conference, Milwaukee, Wisconsin. https://peer.asee.org/6431

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