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Benchmark Evaluations Of Modern Multi Processor Vlsi Ds Pm Ps

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Conference

1998 Annual Conference

Location

Seattle, Washington

Publication Date

June 28, 1998

Start Date

June 28, 1998

End Date

July 1, 1998

ISSN

2153-5965

Page Count

9

Page Numbers

3.120.1 - 3.120.9

Permanent URL

https://peer.asee.org/6938

Download Count

52

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Paper Authors

author page

Jr., Fred O. Simons

author page

Aaron L. Robinson

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Abstract
NOTE: The first page of text has been automatically extracted and included below in lieu of an abstract

1220 Session 1220

Benchmark Evaluations of Modern Multi-Processor VLSI DSPµPs Aaron L. Robinson and Fred O. Simons, Jr. High-Performance Computing and Simulation (HCS) Research Laboratory Electrical Engineering Department Florida A&M University and Florida State University Tallahassee, FL 32316-2175

Abstract - The authors continue their tradition of presenting technical reviews and performance comparisons of the newest multi-processor VLSI DSPµPs with the intention of providing concise focused analyses designed to help established or aspiring DSP analysts evaluate the applicability of new DSP technology to their specific applications. As in the past, the Analog Devices SHARCTM and Texas Instruments TMS320C80 families of DSPµPs will be the focus of our presentation because these manufacturers continue to push the envelop of new DSPµPs (Digital Signal Processing microProcessors) development. However, in addition to the standard performance analyses and benchmark evaluations, the authors will present a new image-processing bench marking technique designed specifically for evaluating new DSPµP image processing capabilities.

1. Introduction

The combination of constantly evolving DSP algorithm development and continually advancing DSPuP hardware have formed the basis for an exponential growth in DSP applications. The increased market demand for these applications and their required hardware has resulted in the production of DSPuPs with very powerful components capable of performing a wide range of complicated operations. Due to the complicated architectures of these new processors, it would be time consuming for even the experienced DSP analysts to review and evaluate these new DSPuPs. Furthermore, the inexperienced DSP analysts would find it even more time consuming, and possibly very difficult to appreciate the significance and opportunities for these new components. Thus, performance comparisons of modern multiprocessor VLSI DSPuPs will be presented in hopes of providing brief time saving reviews for analysts who need to consider these devices for critical new applications. The performance comparisons TM will emphasize the Analog Devices SHARC and the Texas Instruments TMS320C80 and TMS320C60 families. The Motorola DSP96002 will also be included because of its data precision.

Initially, distinguishing architectural features of each of the microprocessors are discussed. Common processor features are then compared and presented in tabular form. The processing speed and power of each of the DSPuPs will then be evaluated in terms of some common digital filtering operations and simple image processing applications. The DSPµPs performance characteristics are presented in easy-to-interpret graphical forms.

It should be noted that the digital filtering operations presented were not chosen as a basis for performance criteria because of their implementation and computational complexities. Instead, the operations were chosen due to the fact that they characterize performance criteria common to almost all DSP applications; e.g., implementation algorithm and data multiplication, addition, quantization, etc. A similar line of logic was applied to the choice of image processing applications. The applications chosen are intended to illustrate a few simple and basic operations involved in point, spatial, and frequency domain image processing while also emphasizing the features of processors specifically adapted to these operations.

2. Modern Parallel DSPuP Candidates and Features

The Texas Instruments TMS320C6201 is a fixed point DSPµP based on the VelociTI ‘C6200 CPU. The processor is capable of 5ns-instruction cycle @ 200 MHz. The architecture features two 16-Bit Multipliers (32-Bit Results), six Arithmetic Logic Units and 1 M-bit of on-chip RAM. In addition to the eight independent functional units, there are 32 32-Bit general purpose registers. The 256-bit wide program memory is capable of fetching eight 32-Bit instructions every cycle. Processor operation at eight instructions per cycle is approximately 10 times faster than other available processors.

Simons, J. F. O., & Robinson, A. L. (1998, June), Benchmark Evaluations Of Modern Multi Processor Vlsi Ds Pm Ps Paper presented at 1998 Annual Conference, Seattle, Washington. https://peer.asee.org/6938

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