BOARD # 297: RET: Acquisition and Retainment of Semiconductor Knowledge among K-12 STEM Teachers

Haniye Mehraban; Jennifer Dawn Cribbs; Erin Dyke; James Stine; John Hu

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Conference: 2025 ASEE Annual Conference & Exposition
Location: Montreal, Quebec, Canada
Publication Date: June 22, 2025
Start Date: June 22, 2025
End Date: August 15, 2025
Conference Session: NSF Grantees Poster Session I
Tagged Topic: NSF Grantees Poster Session
Page Count: 5
Permanent URL: https://peer.asee.org/55662

Jennifer Cribbs, is a Professor in the School of Teaching, Learning and Educational Sciences at Oklahoma State University. She is also the Director for the Center for Research on STEM Teaching and Learning (CRSTL). Dr. Cribbs earned a B.S. in Chemical Engineering at Florida Institute of Technology, a MAT in Mathematics Education at Converse College, and a Ph.D. in Curriculum and Instruction with a focus on Mathematics Education at Clemson University. Her research focus is on mathematics identity and student persistence in STEM. She also explores teachers’ beliefs and practices and their connection to student affect.

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Erin Dyke Oklahoma State University

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James Stine Oklahoma State University orcid.org/0000-0001-8767-390X

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I am a Professor at Oklahoma State University interested in pushing the frontiers of computation within digital logic for general-purpose and application-specific computer architectures. I have interests in logic design for high-speed and low-power arithmetic, VLSI, FPGA, memory architectures, divide and square root implementations, computer architectures, cryptographic implementations, and graphics applications.

I have also developed several design flows for use with Electronic Design Automation (EDA) tools, including the FreePDK with my colleagues Rhett Davis from NC State University and those at the Semiconductor Research Corporation (SRC), several Cadence Design Systems (CDS) flows including the GPDK and MOSIS flows for use with CDS, National Science Foundation-funded OpenRAM, and Mentor Graphics and Synopsys EDA flows. I have also developed design flows for Google, Skywater Technology, IBM, trusted foundry, and the US Air Force. I am committed to use my experience to help others learn these tools and help develop them to further research endeavors for everyone involved.

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John Hu Oklahoma State University orcid.org/0000-0002-6174-8392

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John Hu received his B.S. in Electronics and Information Engineering from Beihang University, Beijing, China, in 2006 and his M.S. and Ph.D. in electrical and computer engineering from the Ohio State University, Columbus, OH, in 2007 and 2010, respectively. He worked as an analog IC designer at Texas Instruments, Dallas, between 2011 and 2012. He was a Member of Technical Staff, IC Design at Maxim Integrated, San Diego, CA, between 2012 and 2016, and a Staff Engineer at Qualcomm, Tempe, AZ, between 2016 and 2019. In 2019, he joined the School of Electrical and Computer Engineering at Oklahoma State University, where he is currently an assistant professor and Jack H. Graham Endowed Fellow of Engineering. His research interests include power management IC design, hardware security, and energy-efficient computing.

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Abstract

This brief summarizes the first two years of participants’ data from a National Science Foundation (NSF) Research Experiences for Teachers (RET) project on Chip Design (Chip-RET). Semiconductor workforce development has become a national priority due to microchips’ importance to our supply chain security, national defense, and technological leadership. K-14 teachers play a pivotal role in exciting, motivating, and preparing students to join various microelectronics-related career pathways. To meet such requirements, K-14 STEM teachers need to receive the necessary training on the subject matter. Our institution proposed the Chip-RET, the first RET program in the US that focused exclusively on integrated circuit design and K-14 semiconductor education. To evaluate the effectiveness of such training, we further developed a custom semiconductor knowledge and literacy test (SKLT), whose content and interpretation have been validated by semiconductor industry experts. Our data reveals that the Year One cohort of ten teachers demonstrated an increase in their mean percentage of correct responses to the SKLT test, from 39% to 65% pre- and post-RET. A follow-up Wilcoxon Rank-Sum Test underscored the significance of this difference, with a W-value of 3 and a p-value less than 0.001. Moreover, a repeat measure of the SKLT test nine months after the Chip-RET training (post-9 months) showed a mean percentage of correct response of 55%, suggesting that participants were able to retain much of their knowledge gained nearly one year after the training. A Wilcoxon Rank-Sum Test from pre- to post-9 months showed a W-value of 12 and a p-value of 0.007, further confirming the gain despite some loss of knowledge over the nine-month period. Finally, the Year Two cohort of another ten teachers also showed an increase from 48% to 69% pre- and post-RET. The post-9 months data is not yet available and will be collected.

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Format

Mehraban, H., & Cribbs, J. D., & Dyke, E., & Stine, J., & Hu, J. (2025, June), BOARD # 297: RET: Acquisition and Retainment of Semiconductor Knowledge among K-12 STEM Teachers Paper presented at 2025 ASEE Annual Conference & Exposition , Montreal, Quebec, Canada . https://peer.asee.org/55662