Yang, Z., & Timorabadi, H. S. (2025, June), BOARD #483: Work In Progress: Remote FPGA Lab - An Interactive Online Environment for Teaching FPGA Development Fundamentals  Paper presented at 2025 ASEE Annual Conference & Exposition , Montreal, Quebec, Canada . 10.18260/1-2--55999

\bibitem{asee_peer_55999}
  Yang, Z., \& Timorabadi, H. S. (2025, June), \emph{BOARD \#483: Work In Progress: Remote FPGA Lab - An Interactive Online Environment for Teaching FPGA Development Fundamentals}
  Paper presented at 2025 ASEE Annual Conference \& Exposition , Montreal, Quebec, Canada .
  10.18260/1-2--55999

Ze Yang and Hamid S Timorabadi P.Eng..  "BOARD #483: Work In Progress: Remote FPGA Lab - An Interactive Online Environment for Teaching FPGA Development Fundamentals".  2025 ASEE Annual Conference & Exposition , Montreal, Quebec, Canada , 2025, June.  ASEE Conferences, 2025.  https://peer.asee.org/55999 Internet.  24 Aug, 2025

\bibitem{asee_peer_55999}
  Ze Yang and Hamid S Timorabadi P.Eng..
  "BOARD \#483: Work In Progress: Remote FPGA Lab - An Interactive Online Environment for Teaching FPGA Development Fundamentals".
  \emph{2025 ASEE Annual Conference \& Exposition , Montreal, Quebec, Canada , 2025, June}.
  ASEE Conferences, 2025.
  https://peer.asee.org/55999 Internet.  24 Aug, 2025

@INPROCEEDINGS{asee_peer_55999
author = "Ze Yang and Hamid S Timorabadi P.Eng."
title = "BOARD \#483: Work In Progress: Remote FPGA Lab - An Interactive Online Environment for Teaching FPGA Development Fundamentals"
booktitle = "2025 ASEE Annual Conference \& Exposition "
year = "2025"
month = "June"
address = "Montreal, Quebec, Canada "
publisher = "ASEE Conferences"
note = {https://peer.asee.org/55999}
number = {10.18260/1-2--55999}
}

TY  - CPAPER
AB  - This paper presents the development and implementation of a remote Field-Programmable Gate
Array (FPGA) lab system, designed to provide students with flexible, remote access to FPGA
hardware. By integrating the Altera DE1 Board with an in-house designed and developed Digital
Design Trainer (DDT) board, the system allows students to engage with FPGA technology from
any location, overcoming the limitations of traditional on-site labs. The remote lab enables real-
time FPGA programming through a web-based interface and live camera feedback, replicating
the in-person lab experience.
In traditional labs, students are typically restricted to two to three hours of lab time, often leaving
insufficient time to explore beyond the core lab assignments. With the Remote FPGA Lab,
students can experiment with course concepts at their own pace, ensuring equitable access to
hands-on FPGA experience regardless of geographic location. This system enhances students'
technical skills and better prepares them for careers in fields requiring custom hardware
solutions.
The initial evaluation of the system has shown promising results. A pilot study with a small
group of students is conducted with valuable feedback, which is used to enhance the system’s
design. In the current semester, students in the digital systems course use the Remote FPGA Lab,
and their feedback is collected to refine further and optimize the system.
AU  - Ze Yang
AU  - Hamid S Timorabadi P.Eng.
CY  - Montreal, Quebec, Canada 
DA  - 2025/06/22
PB  - ASEE Conferences
TI  - BOARD #483: Work In Progress: Remote FPGA Lab - An Interactive Online Environment for Teaching FPGA Development Fundamentals
UR  - https://peer.asee.org/55999
DO  - 10.18260/1-2--55999
ER  -