Circuit-Level Microelectronics Reliability Project to Foster Interdisciplinary Engineering Learning

Nigel Michael Caprotti; Ping-Chuan Wang

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Conference: 2023 ASEE Annual Conference & Exposition
Location: Baltimore , Maryland
Publication Date: June 25, 2023
Start Date: June 25, 2023
End Date: June 28, 2023
Conference Session: Student Division (STDT) Technical Session 3: Student Innovative Practice
Tagged Division: Student Division (STDT)
Page Count: 11
DOI: 10.18260/1-2--43199
Permanent URL: https://peer.asee.org/43199
Download Count: 340

Paper Authors

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Nigel Michael Caprotti State University of New York, New Paltz

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Nigel Caprotti obtained a B.S. in Mechanical Engineering in 2019 from SUNY New Paltz and is slated to receive a M.S. in Electrical Engineering from SUNY New Paltz in Fall of 2023. He currently works at GlobalFoundries as a process engineer.

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Ping-Chuan Wang State University of New York, New Paltz

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Dr. Ping-Chuan Wang is an Assistant Professor in the Division of Engineering Programs at the State University of New York (SUNY) at New Paltz. He received his B.S. from National Tsing-Hua University in Taiwan and M.S. and Eng.Sci.D. in Materials Science and Engineering from Columbia University. Subsequently he joined IBM Microelectronics as an R&D scientist/engineer for a career in the microelectronics industry to develop advanced semiconductor technologies. He joined SUNY New Paltz in 2018 with expertise in materials science and solid mechanics, and with research interests in stress-induced phenomena in engineering materials, microelectronics reliability, additive manufacturing of metals, and interdisciplinary engineering education.

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Abstract

The Microelectronics Reliability course has been offered in the Division of Engineering Programs at SUNY New Paltz as a professional elective since Spring 2020. As one of the pedagogical goals of this one-semester course is to highlight and promote the interdisciplinary nature of semiconductors engineering, students are encouraged to collaborate and contribute their technical knowledge in the realms of electrical and mechanical engineering to study the reliability of computer chips. In the past, this course introduced the degradation mechanism associated with each circuit component separately, including hot-carrier injection in transistors and electromigration in metal interconnects. Individual projects were assigned to model and project the end-of-life wear-out from a specified degradation mechanism. As noted previously, the prior course did not engage direct collaboration between the electrical and mechanical engineering students. Since interdisciplinary collaboration and apt technical communication are necessities in the semiconductor industry, an effective delivery of this course engenders the development of a team-based project in which students in different disciplines can exercise their respective academic knowledge to jointly make reliability assessments. We propose a final group project which studies the overall circuit-level reliability, with each group comprising a mix of two to three mechanical and electrical engineering students. Employing a basic BiCMOS voltage follower, groups are required to conduct circuit-level reliability assessments holistically, tasking students with quantifying the interaction among devices under operation, estimating the degradation of individual components, and proposing strategies to mitigate potential reliability risks. By design, electrical engineering students will be charged with evaluating the circuit on a schematic-level and simulating the circuit operation, and mechanical engineering students will undertake thermal analysis to account for localized Joule heating and estimate temperature distribution in the circuit. Collaboratively across disciplines, the condition of each circuit element under operation can be ascertained. This paper will introduce the design considerations and outline of the group project, as well as demonstrate the feasibility of the holistic reliability assessment using the voltage follower circuit. Plans to evaluate the impact on the learning outcomes from the group project will also be described.

Citation
Format

Caprotti, N. M., & Wang, P. (2023, June), Circuit-Level Microelectronics Reliability Project to Foster Interdisciplinary Engineering Learning Paper presented at 2023 ASEE Annual Conference & Exposition, Baltimore , Maryland. 10.18260/1-2--43199

TY  - CPAPER
AB  - The Microelectronics Reliability course has been offered in the Division of Engineering Programs at SUNY New Paltz as a professional elective since Spring 2020. As one of the pedagogical goals of this one-semester course is to highlight and promote the interdisciplinary nature of semiconductors engineering, students are encouraged to collaborate and contribute their technical knowledge in the realms of electrical and mechanical engineering to study the reliability of computer chips. In the past, this course introduced the degradation mechanism associated with each circuit component separately, including hot-carrier injection in transistors and electromigration in metal interconnects. Individual projects were assigned to model and project the end-of-life wear-out from a specified degradation mechanism. As noted previously, the prior course did not engage direct collaboration between the electrical and mechanical engineering students. Since interdisciplinary collaboration and apt technical communication are necessities in the semiconductor industry, an effective delivery of this course engenders the development of a team-based project in which students in different disciplines can exercise their respective academic knowledge to jointly make reliability assessments. We propose a final group project which studies the overall circuit-level reliability, with each group comprising a mix of two to three mechanical and electrical engineering students. Employing a basic BiCMOS voltage follower, groups are required to conduct circuit-level reliability assessments holistically, tasking students with quantifying the interaction among devices under operation, estimating the degradation of individual components, and proposing strategies to mitigate potential reliability risks. By design, electrical engineering students will be charged with evaluating the circuit on a schematic-level and simulating the circuit operation, and mechanical engineering students will undertake thermal analysis to account for localized Joule heating and estimate temperature distribution in the circuit. Collaboratively across disciplines, the condition of each circuit element under operation can be ascertained. This paper will introduce the design considerations and outline of the group project, as well as demonstrate the feasibility of the holistic reliability assessment using the voltage follower circuit. Plans to evaluate the impact on the learning outcomes from the group project will also be described.
AU  - Nigel Michael Caprotti
AU  - Ping-Chuan Wang
CY  - Baltimore , Maryland
DA  - 2023/06/25
PB  - ASEE Conferences
TI  - Circuit-Level Microelectronics Reliability Project to Foster Interdisciplinary Engineering Learning
UR  - https://peer.asee.org/43199
DO  - 10.18260/1-2--43199
ER  -