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Darp's Digital System Design Curriculum And Peer Reviewed Educational Infrastructure

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Conference

1997 Annual Conference

Location

Milwaukee, Wisconsin

Publication Date

June 15, 1997

Start Date

June 15, 1997

End Date

June 18, 1997

ISSN

2153-5965

Page Count

15

Page Numbers

2.124.1 - 2.124.15

Permanent URL

https://peer.asee.org/6484

Download Count

45

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Paper Authors

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T. Taylor

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T. Egolf

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R. Klenke

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M. Salinas

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J. Stinson

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H. Carter

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Vijay K. Madisetti

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James H. Aylor

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Anthony J. Gadient

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Abstract
NOTE: The first page of text has been automatically extracted and included below in lieu of an abstract

Session 1232

DARPA’s Digital System Design Curriculum and Peer-Reviewed Educational Infrastructure

V. Madisetti, A. Gadient, J. Stinson, J. Aylor, , R. Klenke, H. Carter, T. Egolf, M. Salinas, T. Taylor

RASSP Education & Facilitation Program 5300 International Blvd., N. Charleston, SC 29418

Abstract

As part of DARPA’s $150M Rapid Prototyping of Application Specific Signal Processors (RASSP) program, the RASSP Education & Facilitation (RASSP E&F) team consisting of SCRA, Georgia Institute of Technology, University of Virginia, University of Cincinnati, Raytheon, and Arthur D. Little has developed a new digital system design curriculum and supporting course infrastructure in the form of an electronic archive of instructional material – course modules, labs, projects, and interactive educational CD-ROMs. Included in this electronic archive or digital library are over 200 hours of instructional material suitable for immediate insertion at the undergraduate and graduate levels. To date, over 80 educational institutions have obtained educational material developed by the RASSP E&F team. In this paper, we present the technical goals and rationale, including an Educational Maturity Model (EMM), motivating our efforts. Additional details are available on our WWW server: .

1. Introduction

The Department of Defense Advanced Research Projects Agency (DARPA) sponsored Rapid Prototyping of Application-Specific Signal Processors (RASSP) program is targeted towards the design, prototyping (from concept to product), and procurement, of large embedded digital systems. Examples of systems of interest range from efficiently packaged single-board embedded systems (as found in high-performance workstations using MCMs) to large multi- chassis radar signal processor systems which typically have performance requirements ranging between 20-1000 BFLOPs (billions of floating operations per second) of computational intensity 3 at pixel rates of 10 MHz, within the form constraints of size, weight, and power of 0.05-1.5m , 40-500 Kg, and 1-10 KW, respectively. Boards represent sub-systems, while multi-board configurations can represent complete systems, and involve hardware fabrication, assembly, and integration with application, control and diagnostic software. Clearly, the RASSP program is of strategic importance to industrial and military competitiveness [6].

RASSP promotes a new design methodology for digital systems prototyping that differs from current design practice as taught in our universities and practiced in the past. Figure 1 represents a high-level depiction of current design practice (circa 1993) for large embedded systems with a data processing section and its associated microcontrol. The design process flow diagram starts with a definition of the requirements for the embedded application (e.g., algorithmic requirements). The behavior of the application (e.g., a STAP/SAR radar signal processor

Taylor, T., & Egolf, T., & Klenke, R., & Salinas, M., & Stinson, J., & Carter, H., & Madisetti, V. K., & Aylor, J. H., & Gadient, A. J. (1997, June), Darp's Digital System Design Curriculum And Peer Reviewed Educational Infrastructure Paper presented at 1997 Annual Conference, Milwaukee, Wisconsin. https://peer.asee.org/6484

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