Asee peer logo

Developing Lab Exercises for Logic Circuit Design using FPGAs

Download Paper |

Conference

2018 ASEE Mid-Atlantic Section Spring Conference

Location

Washington, District of Columbia

Publication Date

April 6, 2018

Start Date

April 6, 2018

End Date

April 7, 2018

Tagged Topic

Diversity

Page Count

19

DOI

10.18260/1-2--33891

Permanent URL

https://peer.asee.org/33891

Download Count

1119

Request a correction

Paper Authors

biography

Baha Bachnak The Pennsylvania State University

visit author page

Baha Bachnak is an undergraduate student majoring in Electrical Engineering at The Pennsylvania State University-Harrisburg. He is also a Schreyer Honors Scholar and has research interests in applications of Field-Programmable Gate Arrays (FPGAs).

visit author page

biography

Nashwa Elaraby Pennsylvania State University, Harrisburg, The Capital College

visit author page

Dr. Elaraby is a faculty at Penn State Harrisburg. She received her PhD degree in Electrical and Computer Engineering from Temple University in 2014. She received her B.Sc and M.Sc. in Electrical Engineering from Alexandria University, Egypt.

Her research interests include digital logic design using Field Programmable Gate Arrays for massively parallel data computations, electronic circuit design, and neuronal data processing for Brain Machine Interface applications.

visit author page

Download Paper |

Abstract

An introductory course to digital logic design is a requirement for most electrical and computer engineering (ECE) programs. It is also one of the first technical courses that ECE students are exposed to. Field Programmable Gate Arrays (FPGAs) is a versatile and adaptable technology with many applications ranging from medical image processing to cryptography. Colleges and universities struggle to maintain a feasible four-year program for students due to advances in technology and the need to incorporate new concepts. By combining an FPGA course and a digital logic design course, the number of required credits may be reduced. This paper describes a number of academic approaches to incorporate FPGA design in digital design courses. One approach is the “flipped classroom”, a teaching method wherein students are encouraged to independently learn concepts outside of the classroom and interact heavily in the classroom to solve problems and complete projects. Other methods include online tutorials and take-home experiments, which build onto to this notion of independent and involved learning. In this paper we will describe two laboratory experiments that pave the path to designing a sophomore-level four semester credit hour (SCH) course. The paper will also include the results of a survey used to evaluate student interest in taking such a course and its advantages over traditional courses.

Bachnak, B., & Elaraby, N. (2018, April), Developing Lab Exercises for Logic Circuit Design using FPGAs Paper presented at 2018 ASEE Mid-Atlantic Section Spring Conference, Washington, District of Columbia. 10.18260/1-2--33891

ASEE holds the copyright on this document. It may be read by the public free of charge. Authors may archive their work on personal websites or in institutional repositories with the following citation: © 2018 American Society for Engineering Education. Other scholars may excerpt or quote from these materials with the same citation. When excerpting or quoting from Conference Proceedings, authors should, in addition to noting the ASEE copyright, list all the original authors and their institutions and name the host city of the conference. - Last updated April 1, 2015