Asee peer logo

Development Of A Testbench For Vhdl Projects

Download Paper |


2005 Annual Conference


Portland, Oregon

Publication Date

June 12, 2005

Start Date

June 12, 2005

End Date

June 15, 2005



Conference Session

Lab Experiments & Other Initiatives

Page Count


Page Numbers

10.462.1 - 10.462.11

Permanent URL

Download Count


Request a correction

Paper Authors

author page

Paolo Tamayo

author page

David Florida

author page

Ramakrishna Gottipati

author page

Janos Grantner

Download Paper |

NOTE: The first page of text has been automatically extracted and included below in lieu of an abstract

Development of a Test Bench for VHDL Projects

Janos L. Grantner, Paolo A. Tamayo, Ramakrishna Gottipati, and Dave Florida

Department of Electrical and Computer Engineering Western Michigan University Kalamazoo MI 49008-5329, USA,,,


The objective of the course Digital Design (ECE355) is to develop the skills students need to design and verify digital systems using contemporary tools and devices. ECE 355 is a required course for students majoring in Computer Engineering. Along with combinational logic design, analysis and synthesis of both synchronous and asynchronous sequential circuits are covered in the course. The two major design projects are verified by simulation and implemented using Programmable Logic Devices (PLDs) and Field Programmable Gate Arrays (FPGAs), respectively, using breadboards.

Circuit designs are done in VHDL. In order to prepare the students to work with a professional development environment, the tools HDS Designer, ModelSim, and LeonardoSpectrum by Mentor Graphics along with the Xilinx ISE/WebPack are used to carry out the typical development tasks from describing the functions of the desired circuits in VHDL to physical implementation and verification.

In the graduate course Advanced Microprocessor Interfacing (ECE 605) students also work with the same set of development tools while taking on more challenging projects that are comparable to similar ones carried out in industry.

Prior to committing their designs to a CPLD or FPGA, students need to verify the performance of the circuits by developing a battery of simulation stimuli. A verification environment, referred to as a test bench, has been created to facilitate testing. The test bench is written in Verilog that encapsulates VHDL designs. Standard tests are included in the test bench as well as models of external devices, or controllers that the students’ designs will interface to. The architecture and methodology of the test bench are discussed in the paper in detail.

In the first part of the paper, we briefly outline the key concepts to develop a verification methodology for teaching and research in the digital systems design area. The second and third sections of the paper focus on the test bench and provide for a few examples on how to use it. The fourth part of the paper concludes with a future assessment plan.

“Proceedings of the 2005 American Society for Engineering Education Annual Conference & Exposition Copyright © 2005, American Society for Engineering Education”

Tamayo, P., & Florida, D., & Gottipati, R., & Grantner, J. (2005, June), Development Of A Testbench For Vhdl Projects Paper presented at 2005 Annual Conference, Portland, Oregon.

ASEE holds the copyright on this document. It may be read by the public free of charge. Authors may archive their work on personal websites or in institutional repositories with the following citation: © 2005 American Society for Engineering Education. Other scholars may excerpt or quote from these materials with the same citation. When excerpting or quoting from Conference Proceedings, authors should, in addition to noting the ASEE copyright, list all the original authors and their institutions and name the host city of the conference. - Last updated April 1, 2015