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Digital Signal Processing With The Sharc

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Conference

1996 Annual Conference

Location

Washington, District of Columbia

Publication Date

June 23, 1996

Start Date

June 23, 1996

End Date

June 26, 1996

ISSN

2153-5965

Page Count

6

Page Numbers

1.167.1 - 1.167.6

Permanent URL

https://peer.asee.org/5995

Download Count

1151

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Paper Authors

author page

Rulph Chassaing

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Roderick Ayers

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Abstract
NOTE: The first page of text has been automatically extracted and included below in lieu of an abstract

Session 1220

Digital Signal Processing with the SHARC

Rulph Chassaing / Roderick Ayers Roger Williams University / Naval Undersea Warfare Center Division Bristol, RI 02809/ Newport, RI 02841

Abstract

This paper introduces the use of Analog Devices’ latest generation of floating-point digital signal processors, the Super Harvard Architecture Computer (SHARC). The SHARC is well suited for a wide range of digital signal processing (DSP) applications. It is particularly useful for implementing complex algorithms such as the fast Fourier transform (FFT) and for developing applications requiring multiple processors in order to satisfy large processing requirements. Features of the SHARC along with available hardware and software support tools are presented. Examples in FIR/IIR filtering and the FFT, implemented using both simulation and real-time execution, further illustrate the use of the SHARC.

Introduction

Digital signal processors are special-purpose fast microprocessors with specialized instruction sets appropriate for signal processing. These devices, made possible through advances in integrated circuit technology, are found in a wide range of applications such as telecommunications, speech processing, etc. In recent years, both fixed and floating-point digital signal processors have emerged from a number of companies such as Texas Instruments, Motorola, and Analog Devices. Those digital signal processors now have architectures that facilitate the use of high-level language compilers. C has become very popular as the high- level language of choice. The use of a high-level language often results in a substantial reduction in execution speed. Alternatively, carefully prepared assembly language programs produce faster executable code, but they are more difficult to document and maintain. The compromise is to code time-critical routines in assembly language that can be called from C. Companies such as Ixthos provide libraries of optimized functions for the SHARC that can be called from C.

Over the last ten years, senior students at Roger Williams University (RWU) have implemented a wide range of real-time DSP applications in areas such as communications, controls, and adaptive and multirate filtering. Those applications, based on both Texas Instruments’ floating-point TMS320C30 and fixed-point TMS320C25 digital signal processors, are described in references 1 and 2.

Investigation of the SHARC was undertaken at the Naval Undersea Warfare Center (NUWC) to determine its suitability for large processing requirements.

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Chassaing, R., & Ayers, R. (1996, June), Digital Signal Processing With The Sharc Paper presented at 1996 Annual Conference, Washington, District of Columbia. https://peer.asee.org/5995

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