Gatson, D. M., & Barnes, R. D. (2022, March), DRIVING GPIO PINS WITH RISC-V INSTRUCTION SET ARCHITECTURE  Paper presented at 2022 ASEE Gulf Southwest Annual Conference, Prairie View, Texas. 10.18260/1-2--39174

\bibitem{asee_peer_39174}
  Gatson, D. M., \& Barnes, R. D. (2022, March), \emph{DRIVING GPIO PINS WITH RISC-V INSTRUCTION SET ARCHITECTURE}
  Paper presented at 2022 ASEE Gulf Southwest Annual Conference, Prairie View, Texas.
  10.18260/1-2--39174

Darius Miles Gatson and Ryan Duane Barnes.  "DRIVING GPIO PINS WITH RISC-V INSTRUCTION SET ARCHITECTURE".  2022 ASEE Gulf Southwest Annual Conference, Prairie View, Texas, 2022, March.  ASEE Conferences, 2022.  https://peer.asee.org/39174 Internet.  20 Jan, 2025

\bibitem{asee_peer_39174}
  Darius Miles Gatson and Ryan Duane Barnes.
  "DRIVING GPIO PINS WITH RISC-V INSTRUCTION SET ARCHITECTURE".
  \emph{2022 ASEE Gulf Southwest Annual Conference, Prairie View, Texas, 2022, March}.
  ASEE Conferences, 2022.
  https://peer.asee.org/39174 Internet.  20 Jan, 2025

@INPROCEEDINGS{asee_peer_39174
author = "Darius Miles Gatson and Ryan Duane Barnes"
title = "DRIVING GPIO PINS WITH RISC-V INSTRUCTION SET ARCHITECTURE"
booktitle = "2022 ASEE Gulf Southwest Annual Conference"
year = "2022"
month = "March"
address = "Prairie View, Texas"
publisher = "ASEE Conferences"
note = {https://peer.asee.org/39174}
number = {10.18260/1-2--39174}
}

TY  - CPAPER
AB  - In this paper, we are demonstrating the use of RISC-V assembly code wrapped in C code to operate a 4-bit full adder. This project was implemented as a partial fulfillment of our Computer Architecture (COSC 3341) course project where we learned about the latest open source RISC-V Instruction Set Architecture (ISA). To implement this project, we used the SN74LS283N 4-bit full adder IC, the SiFive HiFive 1 Rev B board that hosts a 32-bit RISC-V processor, breadboard, LEDs, and few resistors. To program the circuit, we used Visual Studio Code with the PlatformIO extension to allow deployment and debugging of the RISC-V assembly code on the HiFive board. The goal of the project was to demonstrate the 4-bit full adder truth table operation by cycling through the different possible inputs and demonstrating the adder output using LED lights. The input to the adder was driven by the board GPIO pins that were enabled through the RISC-V assembly code. Using the SiFive HiFive 1 Rev B manuals, we identified the base memory addresses to access the GPIO pins and the offsets of the individual pins. Through experimentation and debugging of our assembly code, we were able to see the effect of running the code using the debug mode which is un-optimized code, and the effect of pre-built optimized binary code. The un-optimized code ran the circuit in a deterministic way and the output was what we expected, while the optimized code scrambled the code due to the reordering of the instructions and out-of-order execution and the output was non-deterministic. The optimized code had a GPIO pin stay on for the duration of the truth table operation and skewed the results because of it. The un-optimized code, in debug mode, had no GPIO pin held HIGH for the entire truth table operation and the GPIO pins held HIGH and LOW when expected. 
AU  - Darius Miles Gatson
AU  - Ryan Duane Barnes
CY  - Prairie View, Texas
DA  - 2022/03/16
PB  - ASEE Conferences
TI  - DRIVING GPIO PINS WITH RISC-V INSTRUCTION SET ARCHITECTURE
UR  - https://peer.asee.org/39174
DO  - 10.18260/1-2--39174
ER  -