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Effectiveness Of Karnaugh Mapplet Use In Student Learning Of Digital Logic Skills

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Conference

2005 Annual Conference

Location

Portland, Oregon

Publication Date

June 12, 2005

Start Date

June 12, 2005

End Date

June 15, 2005

ISSN

2153-5965

Conference Session

Computing Tools for Engineering Education

Page Count

10

Page Numbers

10.514.1 - 10.514.10

Permanent URL

https://peer.asee.org/14557

Download Count

28

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Paper Authors

author page

Phillip Misna

author page

Erica Liszewski

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Abstract
NOTE: The first page of text has been automatically extracted and included below in lieu of an abstract

Effectiveness of Karnaugh Mapplet Use in Student Learning of Digital Logic Skills Phillip A. Mlsna, Erica Liszewski Electrical Engineering / Computer Science PO Box 15600, Northern Arizona University Flagstaff, AZ USA Phillip.Mlsna@nau.edu

Introduction

Our core course in digital logic at Northern Arizona University (NAU) aims to develop a set of key skills needed throughout the electrical and computer engineering curriculum. Digital logic covers the analysis and design of combinational and sequential digital logic circuits using the standard principles of Boolean algebra. The subject forms a vital part of the technical foundation that enables our students to contribute to the field of modern digital hardware. Students are often called upon in later courses to apply a key set of digital logic analysis and design skills to the advanced material being covered. Those who are weak in these skills are at a decided disadvantage.

Experience at NAU indicates that many students who do well in the digital logic course often have trouble applying this material in later courses. Colleagues at other universities have expressed similar concerns. This indicates that their knowledge is often rather fragile. There are several likely causes: 1) Insufficient student practice with critical skills and concepts. Most students require extensive practice to develop consistency, accuracy, and speed. In the traditional course, practice primarily takes the form of assigned homework problems. 2) Long delays in providing students individual constructive feedback about their work. The traditional homework cycle can interfere with the ability to identify and address student errors quickly and so delays the learning process. Incorrect techniques and bad habits often become entrenched before the instructor notices. 3) Spotty constructive feedback. The burden is traditionally placed heavily upon the student to seek help and clarification. Most students tend not to seek assistance until the situation has persisted for some time.

Approach

The minimization of Boolean expressions using the Karnaugh map (K-map) is a critical skill that is developed and used throughout the course. Since many students have difficulty with K-map techniques, we decided to target these skills first. The primary goal has been to provide a means for extensive student practice with K-map problems while providing immediate constructive feedback. Sum-of-products (SOP) and product-of-sums (POS) forms should be given equal emphasis.

Proceedings of the 2005 American Society for Engineering Education Annual Conference & Exposition Copyright  2005, American Society for Engineering Education

Misna, P., & Liszewski, E. (2005, June), Effectiveness Of Karnaugh Mapplet Use In Student Learning Of Digital Logic Skills Paper presented at 2005 Annual Conference, Portland, Oregon. https://peer.asee.org/14557

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