Li, J., & Li, C., & Son, J. S., & Kuang, W., & Gil, E. (2020, June), Effectiveness of Using MyFPGA Platform for Teaching Digital Logic  Paper presented at 2020 ASEE Virtual Annual Conference Content Access, Virtual On line . 10.18260/1-2--34505

\bibitem{asee_peer_34505}
  Li, J., \& Li, C., \& Son, J. S., \& Kuang, W., \& Gil, E. (2020, June), \emph{Effectiveness of Using MyFPGA Platform for Teaching Digital Logic}
  Paper presented at 2020 ASEE Virtual Annual Conference Content Access, Virtual On line .
  10.18260/1-2--34505

Junfei Li P.E., Cara Li, Jae Sok Son, Weidong Kuang, and Edgar Gil.  "Effectiveness of Using MyFPGA Platform for Teaching Digital Logic".  2020 ASEE Virtual Annual Conference Content Access, Virtual On line , 2020, June.  ASEE Conferences, 2020.  https://peer.asee.org/34505 Internet.  15 Dec, 2024

\bibitem{asee_peer_34505}
  Junfei Li P.E., Cara Li, Jae Sok Son, Weidong Kuang, and Edgar Gil.
  "Effectiveness of Using MyFPGA Platform for Teaching Digital Logic".
  \emph{2020 ASEE Virtual Annual Conference Content Access, Virtual On line , 2020, June}.
  ASEE Conferences, 2020.
  https://peer.asee.org/34505 Internet.  15 Dec, 2024

@INPROCEEDINGS{asee_peer_34505
author = "Junfei Li P.E., Cara Li, Jae Sok Son, Weidong Kuang, and Edgar Gil"
title = "Effectiveness of Using MyFPGA Platform for Teaching Digital Logic"
booktitle = "2020 ASEE Virtual Annual Conference Content Access"
year = "2020"
month = "June"
address = "Virtual On line "
publisher = "ASEE Conferences"
note = {https://peer.asee.org/34505}
number = {10.18260/1-2--34505}
}

TY  - CPAPER
AB  - Accompanying electric circuits and computer programming, digital logic is deemed one of the most essential parts of any Electrical and Computer Engineering curriculum, so student success in the course is critical. Furthermore, research shows that the academic performance of students is heavily dependent upon student engagement, which is believed to increase with classroom strategies such as flipped-classrooms, cooperative learning, project-based learning, and virtual labs. The University of Texas Rio Grande Valley (UTRGV) is a Hispanic serving institution with distributive campuses, where many of the students work part-time. With consideration of the special needs of our students and the latest developments in engineering education, this study focuses on our recent experience of teaching digital logical using MyFPGA, online FPGA platform.
We first introduce the MyFPGA platform in this paper. Developed by one of the authors of this paper, this web-based design features I/O interfacing circuits with an Intel FPGA hardware board as well as API web services with the Intel Quartus II design software. The platform provides 24/7 real-time hardware design experience at students’ fingertips, requiring only a web browser and internet access.  It exposes the students to a complete engineering design cycle that includes problem specification, block diagram design, HDL source code design, simulation and hardware verification, trouble shooting and evaluation, and reporting.  We consider different cases of the platform usage in two digital logic courses. To evaluate the effectiveness of the student learning experience, data is collected using outcome assessments, student feedback and self-evaluations, instructor observations, and comparative studies.  Preliminary results confirmed the effectiveness of the online digital design platform. We have also identified a few pitfalls, such as instructors’ initial reluctance in adopting the platform and students’ first perception of the platform as a pure simulation tool. Based on the studies, recommendations are made to identify the best practices in the utilization of the platform to better serve Electrical and Computer Engineering majors and secondary school students interested in the general STEM fields.


AU  - Junfei Li P.E.
AU  - Cara Li
AU  - Jae Sok Son
AU  - Weidong Kuang
AU  - Edgar Gil
CY  - Virtual On line 
DA  - 2020/06/22
PB  - ASEE Conferences
TI  - Effectiveness of Using MyFPGA Platform for Teaching Digital Logic
UR  - https://peer.asee.org/34505
DO  - 10.18260/1-2--34505
ER  -