New Orleans, Louisiana
June 26, 2016
June 26, 2016
August 28, 2016
Electrical and Computer
On-chip networking concepts, which are central to multicore microprocessor design, are often taught using textbooks and the standard lecture model, as it is difficult to provide interactive learning opportunities and hands-on assignments. Available on-chip network simulators typically focus on research-level accuracy and are not suitable for novices or students. Meanwhile, with each new chip generation, the importance of the on-chip interconnect grows. Career opportunities in computer architecture will increasingly rely on an understanding of the chip's communication substrate. The lack of interactive, approachable tools thus leaves students with a gap in their computer architecture education in an increasingly multicore industry.
In this paper, we present ENoCS, the Educational Network-on-Chip Simulator, which allows users of all levels of expertise to explore the on-chip network environment and see the inner workings of the on-chip communication substrate and all of its components. ENoCS contains multiple topologies and network options, as well as multiple traffic patterns for testing. ENoCS also shows microarchitectural details, including router structure, packet breakdown, and routing tables. We also present methods for incorporating ENoCS into an existing computer architecture course curriculum and an evaluation of its effectiveness in a small senior/graduate-level course. Students in the evaluated course who used the tool showed an increased competency in the concepts, as well as interest in using the tool further. While the sample size was small, it demonstrates the promise of using the ENoCS tool in the classroom. The simulator is available on-line for public use at https://github.com/ProfACarpenter/ENoCS.
Viglucci, P. W., & Carpenter, A. P. (2016, June), ENoCS: An Interactive Educational Network-on-Chip Simulator Paper presented at 2016 ASEE Annual Conference & Exposition, New Orleans, Louisiana. 10.18260/p.26720
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