Hayne, R. J., & Moore, J. I. (2015, June), Evolution of the Instructional Processor  Paper presented at 2015 ASEE Annual Conference & Exposition, Seattle, Washington. 10.18260/p.24039

\bibitem{asee_peer_24039}
  Hayne, R. J., \& Moore, J. I. (2015, June), \emph{Evolution of the Instructional Processor}
  Paper presented at 2015 ASEE Annual Conference \& Exposition, Seattle, Washington.
  10.18260/p.24039

Ronald J. Hayne and John I. Moore Jr..  "Evolution of the Instructional Processor".  2015 ASEE Annual Conference & Exposition, Seattle, Washington, 2015, June.  ASEE Conferences, 2015.  https://peer.asee.org/24039 Internet.  14 Jan, 2025

\bibitem{asee_peer_24039}
  Ronald J. Hayne and John I. Moore Jr..
  "Evolution of the Instructional Processor".
  \emph{2015 ASEE Annual Conference \& Exposition, Seattle, Washington, 2015, June}.
  ASEE Conferences, 2015.
  https://peer.asee.org/24039 Internet.  14 Jan, 2025

@INPROCEEDINGS{asee_peer_24039
author = "Ronald J. Hayne and John I. Moore Jr."
title = "Evolution of the Instructional Processor"
booktitle = "2015 ASEE Annual Conference \& Exposition"
year = "2015"
month = "June"
address = "Seattle, Washington"
publisher = "ASEE Conferences"
note = {https://peer.asee.org/24039}
number = {10.18260/p.24039}
}

TY  - CPAPER
AB  -                         Evolution of the Instructional ProcessorAbstractMost modern commercial microprocessors are too complex to be used as introductory examplesof processor design. Many digital design courses and texts use hardware description languagemodels of these processors, but they are often ad hoc and don't divide the architecture intoteachable subsets. What is needed is a basic processor with sufficient complexity to illustratemajor design elements that can be modified, programmed, and tested.An instructional processor has been developed for use as a design example in an AdvancedDigital Systems course. The initial architecture provides sufficient complexity to demonstratefundamental programming concepts such as data transfer, counting, indexing, and looping. Theentire system is modeled in VHDL and can be simulated to demonstrate operation of theprocessor. Additionally, the processor design can be synthesized and implemented in hardwareon a field programmable gate array (FPGA). Students have the opportunity to interact withprograms running via simulation or on actual hardware.A collaborative project between Electrical Engineering and Computer Science has added newcapabilities to the instructional processor, which provide improved higher-level language supportfor a Compiler Design course. Memory has been expanded and reorganized with a new memorymodel and additional addressing modes. Machine code from a compiler or assembler can nowbe uploaded without modification of the VHDL model. Branch instructions have also beenexpanded, including support for subroutines, allowing for better program design and memoryutilization.The processor expansions have been kept simple enough to allow teaching of the architecture infunctional subsets. The data path contains the memory, registers, arithmetic logic unit, andinterconnecting buses. The controller implements the fetch, decode, and execute sequences foreach category of instructions. The more capable instructional processor can still be implementedon a basic Spartan 3 FPGA, utilizing approximately 50% of available logic, while takingadvantage of all available block RAM.The instructional processor is now in its third evolution with additional capabilities, an updatedcontroller design, and a new memory model. Homework assignments demonstrate that studentscan successfully design modifications to the processor and test them via program simulation.Feedback is very positive that the VHDL model and FPGA implementation of the processorillustrate fundamental design concepts without unnecessary complexity. The expanded projectcontinues to achieve its goal as a valuable instructional tool for Advanced Digital Systems withfuture utilization as an implementation platform for a Compiler Design course.
AU  - Ronald J. Hayne
AU  - John I. Moore Jr.
CY  - Seattle, Washington
DA  - 2015/06/14
PB  - ASEE Conferences
TI  - Evolution of the Instructional Processor
UR  - https://peer.asee.org/24039
DO  - 10.18260/p.24039
ER  -