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Evolution of the Instructional Processor

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2015 ASEE Annual Conference & Exposition


Seattle, Washington

Publication Date

June 14, 2015

Start Date

June 14, 2015

End Date

June 17, 2015





Conference Session

Software and Programming

Tagged Division

Computers in Education

Page Count


Page Numbers

26.702.1 - 26.702.9



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Paper Authors


Ronald J. Hayne The Citadel

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Ronald J. Hayne is an Associate Professor in the Department of Electrical and Computer Engineering at The Citadel. He received his B.S. in Computer Science from the United States Military Academy, his M.S. in Electrical Engineering from the University of Arizona, and his Ph.D. in Electrical Engineering from the University of Virginia. Dr. Hayne's professional areas of interest include digital systems design and hardware description languages. He is a retired Army Colonel with experience in academics and Defense laboratories.

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John I. Moore Jr. The Citadel

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John I. Moore, Jr. is a Professor in the Department of Mathematics and Computer Science at The Citadel. He received his B.S. in Mathematics from The Citadel, his M.S. in Computer Science from Georgia Institute of Technology, and his Ph.D. in Mathematics from the University of South Carolina. Dr. Moore has a wide range of experience in both industry and academia, with specific expertise in the areas of object-oriented technology, mobile applications, programming language translators, graph theory, and e-commerce.

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Evolution of the Instructional ProcessorAbstractMost modern commercial microprocessors are too complex to be used as introductory examplesof processor design. Many digital design courses and texts use hardware description languagemodels of these processors, but they are often ad hoc and don't divide the architecture intoteachable subsets. What is needed is a basic processor with sufficient complexity to illustratemajor design elements that can be modified, programmed, and tested.An instructional processor has been developed for use as a design example in an AdvancedDigital Systems course. The initial architecture provides sufficient complexity to demonstratefundamental programming concepts such as data transfer, counting, indexing, and looping. Theentire system is modeled in VHDL and can be simulated to demonstrate operation of theprocessor. Additionally, the processor design can be synthesized and implemented in hardwareon a field programmable gate array (FPGA). Students have the opportunity to interact withprograms running via simulation or on actual hardware.A collaborative project between Electrical Engineering and Computer Science has added newcapabilities to the instructional processor, which provide improved higher-level language supportfor a Compiler Design course. Memory has been expanded and reorganized with a new memorymodel and additional addressing modes. Machine code from a compiler or assembler can nowbe uploaded without modification of the VHDL model. Branch instructions have also beenexpanded, including support for subroutines, allowing for better program design and memoryutilization.The processor expansions have been kept simple enough to allow teaching of the architecture infunctional subsets. The data path contains the memory, registers, arithmetic logic unit, andinterconnecting buses. The controller implements the fetch, decode, and execute sequences foreach category of instructions. The more capable instructional processor can still be implementedon a basic Spartan 3 FPGA, utilizing approximately 50% of available logic, while takingadvantage of all available block RAM.The instructional processor is now in its third evolution with additional capabilities, an updatedcontroller design, and a new memory model. Homework assignments demonstrate that studentscan successfully design modifications to the processor and test them via program simulation.Feedback is very positive that the VHDL model and FPGA implementation of the processorillustrate fundamental design concepts without unnecessary complexity. The expanded projectcontinues to achieve its goal as a valuable instructional tool for Advanced Digital Systems withfuture utilization as an implementation platform for a Compiler Design course.

Hayne, R. J., & Moore, J. I. (2015, June), Evolution of the Instructional Processor Paper presented at 2015 ASEE Annual Conference & Exposition, Seattle, Washington. 10.18260/p.24039

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