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Fault Tolerant Multicomputer Design With Dsp96002 Microprocessors

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Conference

1996 Annual Conference

Location

Washington, District of Columbia

Publication Date

June 23, 1996

Start Date

June 23, 1996

End Date

June 26, 1996

ISSN

2153-5965

Page Count

11

Page Numbers

1.215.1 - 1.215.11

Permanent URL

https://peer.asee.org/6055

Download Count

13

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Paper Authors

author page

Alan D. George

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Abstract
NOTE: The first page of text has been automatically extracted and included below in lieu of an abstract

Session 1220

Fault-Tolerant Multicomputer Design with DSP96002 Microprocessors

Alan D. George High-performance Computing and Simulation (HCS) Research Laboratory FAMU-FSU College of Engineering Florida State University and Florida A&M University

The objective of this paper is to overview the design and performance results of a fault-tolerant multicomputer architecture implemented with DSP96002 microprocessors. Topics include processor architectural features, multicomputer system design, design extensions, and test results.

Introduction The processing and input/output capabilities of conventional microprocessors and digital signal processors (DSPs) continue to improve because of architectural enhancements such as superscalar processing, pipelining, redundant buses and functional units, and higher clock rates. However, while these processors have improved, they have not been able to keep pace with the increasing demands and complexity of new signal processing algorithms and applications. Thus, as in all scientific computing arenas addressing high-end and grand-challenge problems, the need for shared-memory multiprocessors and distributed-memory multicomputer architectures is clear. Some conventional microprocessors and DSPs are more readily and easily adapted to use in the design and construction of a parallel processing machine due to their support in hardware for interfacing and scheduling functions. One particularly flexible processor for signal processing applications is the Motorola DSP96002, a 32-bit floating-point DSP featuring an extended Harvard architecture, three 4GW address spaces (program, data X, and data Y), on-chip RAM and ROM, superscalar support for concurrent multiply, add, subtract, and move operations, a highly-optimized pipelined program control unit, and two sets of address, data, and control buses forming ports A and B with built-in host and interprocessor interface logic. By combining a number of these floating- point processors into a dual-mode linear-array topology with passive hardware redundancy, a fault-tolerant DSP-based parallel architecture has been designed and developed to satisfy a number of real-time signal processing requirements. This paper illustrates the use of advanced microprocessors in the design and development of scaleable and high-performance embedded computers based on a dual-mode multicomputer architecture. Topics include an overview of DSP architectural features and the DSP96002 in particular, multicomputer system design, design extensions for dual-mode functionality, prototype test results via high-fidelity system emulation, and finally conclusions and future research.

Digital signal processors One of the most important recent developments in scientific computing in general and signal processing in particular is the digital signal processor (DSP). These microprocessor devices are designed to perform numerically-intensive real-time signal processing tasks at an optimum rate. They typically consist of a single chip often supplemented with support chips for I/O, A/D conversion, D/A conversion, and additional off-chip memory. While designed with performance in mind, they are considered weaker in functionality and programming convenience than their general-purpose microprocessor counterparts. This situation, however, is rapidly improving8-9. In order to achieve the performance improvements typical of these microprocessors, a number of architectural strategies have been employed. Three of the most important techniques that are often used are specialized arithmetic hardware for high-speed calculations, multiple buses for parallel memory access, and internal pipelining for parallel execution of instructions. Perhaps the most fundamental characteristic of DSPs is their incorporation and integration of high-performance hardware multipliers and adders. Most devices are capable of performing a multiply-accumulate (i.e. a simultaneous multiply and addition) in a single instruction cycle, often concurrently with other operations such as instruction and data fetch. DSPs can be categorized by the method used for arithmetic storage and manipulation, either fixed-point or floating-point. While fixed-point systems are simpler

1996 ASEE Annual Conference Proceedings

George, A. D. (1996, June), Fault Tolerant Multicomputer Design With Dsp96002 Microprocessors Paper presented at 1996 Annual Conference, Washington, District of Columbia. https://peer.asee.org/6055

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