Asee peer logo

Filter Design And Implementation Using The Tms320 C6x Interfaced With Matlab

Download Paper |

Conference

2000 Annual Conference

Location

St. Louis, Missouri

Publication Date

June 18, 2000

Start Date

June 18, 2000

End Date

June 21, 2000

ISSN

2153-5965

Page Count

7

Page Numbers

5.299.1 - 5.299.7

Permanent URL

https://peer.asee.org/8382

Download Count

692

Request a correction

Paper Authors

author page

Walter J. Gomes III

author page

Rulph Chassaing

Download Paper |

Abstract
NOTE: The first page of text has been automatically extracted and included below in lieu of an abstract

Session 1320

Filter Design and Implementation Using the TMS320C6x Interfaced with MATLAB

Walter J. Gomes III, Rulph Chassaing University of Massachusetts Dartmouth

Abstract

This paper describes the design and real-time implementation of FIR and IIR filters using MATLAB interfaced directly with the TMS320C6x (C6x) digital signal processor. An FIR or IIR filter can be readily designed using MATLAB’s graphical filter designer SPTOOL to generate a set of coefficients associated with a desired filter's characteristics. These coefficients are included into a generic filter program transparent to the user. Within SPTOOL, the filter’s frequency response is plotted on the PC monitor. By modifying SPTOOL, the authors provide a button located on the toolbar to implement the desired filter in real-time on the C6x. Another button is provided to obtain a real-time implementation of the filter on the TMS320C31 on board a DSP Starter Kit (DSK)1,2. The authors have developed the support files required to duplicate these results, and they are available to anyone interested. Similar techniques can be developed to interface MATLAB with different digital signal processors.

Introduction

Digital signal processors are currently used for a wide range of applications from communications and controls to speech processing. They are found in cellular phones, fax/modems, disk drives, etc. They continue to be more and more successful because of the availability of low-cost support tools. DSP-based systems can be readily reprogrammed for a different application.

The C6x is Texas Instruments’ (TI) highest performance processor based on the Very Long Instruction Word (VLIW) architecture. This type of architecture is very suitable for multitasking. The internal program memory of the C6x is structured as “fetch packets” with a 256-bit instruction and a 256-bit bus. As a result, a word (VLIW) can be fetched every cycle. For example, a C6x with a 200 MHz clock is capable of fetching eight 32-bit instructions, which forms a fetch packet, every 5 ns.

The C6x supports a 32-bit address bus to address 4G bytes, and two sets of sixteen 32-bit registers. It contains eight execution units composed of six ALU’s and two multiplier units.

On-chip memory is available as program cache, data cache, and RAM/cache. The exact amount and configuration of memory depends on the specific member of the C6x family of processors. For example, the fixed-point C6211 (which is on-board TI’s popular C6x DSK), has two Level-1 (L1)

Gomes III, W. J., & Chassaing, R. (2000, June), Filter Design And Implementation Using The Tms320 C6x Interfaced With Matlab Paper presented at 2000 Annual Conference, St. Louis, Missouri. https://peer.asee.org/8382

ASEE holds the copyright on this document. It may be read by the public free of charge. Authors may archive their work on personal websites or in institutional repositories with the following citation: © 2000 American Society for Engineering Education. Other scholars may excerpt or quote from these materials with the same citation. When excerpting or quoting from Conference Proceedings, authors should, in addition to noting the ASEE copyright, list all the original authors and their institutions and name the host city of the conference. - Last updated April 1, 2015