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Implementing Serial Communication for the Instructional Processor

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2020 ASEE Virtual Annual Conference Content Access


Virtual On line

Publication Date

June 22, 2020

Start Date

June 22, 2020

End Date

June 26, 2021

Conference Session

Computers in Education Division Technical Session 4: Digital Learning Part II

Tagged Division

Computers in Education

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Paper Authors


Ronald J. Hayne The Citadel

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Ronald J. Hayne is a Professor in the Department of Electrical and Computer Engineering at The Citadel. He received his B.S. in Computer Science from the United States Military Academy, his M.S. in Electrical Engineering from the University of Arizona, and his Ph.D. in Electrical Engineering from the University of Virginia. Dr. Hayne's professional areas of interest include digital systems design and hardware description languages. He is a retired Army Colonel with experience in academics and Defense laboratories.

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An Instructional Processor has been developed for use as a design example in an Advanced Digital Systems course. The architecture is modelled in VHDL and can be simulated using Xilinx design tools to demonstrate operation of the processor. A basic microcontroller is then created by adding memory-mapped input/output (I/O). The system can be synthesized and implemented in hardware on a field programmable gate array (FPGA). The goal of this project was to add serial communication capabilities to the Instructional Processor via software and hardware. The enhanced microcontroller can then be interfaced with multiple peripheral devices.

Serial communication is widely used to connect external devices to computer systems. The communication interface, which receives and transmits serial data, is commonly known as a UART (universal asynchronous receiver transmitter). The serial data format uses standard bit timing and framing. The protocol can be implemented in software using timing loops and basic bit shifting, but will be limited to half-duplex (only one direction at a time). A full-duplex hardware implementation requires interfacing with internal processor registers and memory.

While VHDL models of hardware UARTs exist, they are often presented as stand-alone devices or intellectual property (IP) cores that connect to proprietary bus architectures. The approach for this project was to adapt a UART model, based on the MC6811, to the memory-mapped I/O interface developed for the Instructional Processor. This implementation allows direct access to the UART data registers (receive and transmit), status register (flags), and control register (baud rate). Test programs, written in assembly language, were used to test the communication protocol and timing via VHDL simulation. The FPGA implementation was also tested using a PC-based serial communication terminal.

A software UART was first developed using timing loops and shift commands. Two memory-mapped registers were used to implement the receiver and transmitter, connected to I/O pins receive (RxD) and transmit (TxD). Half-duplex communication was demonstrated by receiving a message, storing it in a table, and then retransmitting it. A hardware UART was implemented and tested to enable full-duplex communication. During simulation, an error in the original transmitter module was discovered and corrected, allowing for simultaneous receiving and retransmission of a message. The FPGA microcontroller was able to communicate with several serial devices at various baud rates.

This project successfully added serial communication capabilities to the Instructional Processor. Software and hardware implementations were developed and tested using VHDL and a Xilinx FPGA. The UART has now been added to the processor design example in the Advanced Digital Systems course, giving students an in-depth look at both the internal details and external interfacing of a real-life system. Feedback has been very positive that the simulation and microcontroller implementation help illustrate fundamental design concepts reinforced by actual functioning hardware.

Hayne, R. J. (2020, June), Implementing Serial Communication for the Instructional Processor Paper presented at 2020 ASEE Virtual Annual Conference Content Access, Virtual On line . 10.18260/1-2--34784

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