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Incorporating Soft Core And Hard Core Processors In Capstone Design Courses

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Conference

2009 Annual Conference & Exposition

Location

Austin, Texas

Publication Date

June 14, 2009

Start Date

June 14, 2009

End Date

June 17, 2009

ISSN

2153-5965

Conference Session

Embedded System Design

Tagged Division

Electrical and Computer

Page Count

8

Page Numbers

14.724.1 - 14.724.8

Permanent URL

https://peer.asee.org/5448

Download Count

247

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Paper Authors

author page

Wagdy Mahmoud University of the District of Columbia

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Abstract
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Incorporating Soft Core and Hard Core Processors in Capstone Design Courses Wagdy H Mahmoud University of the District of Columbia wmahmoud@udc.edu

Abstract This paper provides details of our electrical engineering program efforts to introduce sot and hard core processors and the concept of SoC in senior-level and senior-design courses. The paper provides details of laboratory exercises and a senior project that is implemented using both soft core and hard core processors on three different FPGA boards. Advantages and disadvantages of each of these implementations will also be presented. The paper will also detail the challenges involved in using continually-evolving embedded processing tools and the efforts made to reduce their learning times.

Introduction The Accreditation Board for Engineering and Technology (ABET) requires providing students with a significant hands-on design experience. Graduating electrical engineering students should have the ability to design, test, and verify the correctness of operation of systems, subsystems, and components for real-time application.

The aggressive advancement of electronic design automation (EDA) tools coupled with the continual evolution of the semiconductor industry in terms of higher transistor densities and smaller process geometries has made it possible for design engineers to develop high performance systems-on-chip (SoC) designs for a verity of compute-intensive applications and to implement such systems on reconfigurable logic Field Programmable Gate Arrays (FPGA). The main characteristics of such complex system include: a) the use high level languages programs in designing complex systems, embedded controllers and applications; b) extensive use of intellectual property (IP) cores; b) employ hardware/software (HW/SW) co-design principles; and c) the use soft core and/or hard core embedded processors [6].

Contemporary Electronic Design Automation (EDA) industry projects exhibits the following trends: a) Increased design complexities, b) Shorter time to market, c) Increased dependency on Intellectual Property (IP) cores, d) Hardware/software co-design, and e) System on a Chip (SOC). The UDC electrical engineering program is increasing its effort to produce electrical engineers who can fulfill the needs and demands of the EDA industry.

The UDC electrical engineering senior projects employ many software packages and a selected set of FPGA boards. The software tools used in this research include the Xilinx Integrated System Environment (ISE), Xilinx embedded design kit (EDK), Xilinx ChipScope, and ModelSim from Mentor Graphics. The embedded processing system systems are based on PowerPCTM405 hard core processors and MicroBlazeTM soft core processor. The Field programmable gate array (FPGA) boards are based on the Spartan-3ETM, The Virtex II ProTM, and VirtexTM 4 FPGA chips. The ISE allows the design of complex digital systems and their

Mahmoud, W. (2009, June), Incorporating Soft Core And Hard Core Processors In Capstone Design Courses Paper presented at 2009 Annual Conference & Exposition, Austin, Texas. https://peer.asee.org/5448

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