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Incorporating System Level Design Tools Into Upper Level Digital Design And Capstone Courses

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Conference

2007 Annual Conference & Exposition

Location

Honolulu, Hawaii

Publication Date

June 24, 2007

Start Date

June 24, 2007

End Date

June 27, 2007

ISSN

2153-5965

Conference Session

Design in the ECE Curriculum

Tagged Division

Electrical and Computer

Page Count

10

Page Numbers

12.875.1 - 12.875.10

Permanent URL

https://peer.asee.org/2735

Download Count

67

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Paper Authors

biography

Wagdy Mahmoud University of the District of Columbia

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Abstract
NOTE: The first page of text has been automatically extracted and included below in lieu of an abstract

Incorporating System-Level Design Tools into upper-Level Digital Design and Capstone Courses

Abstract

This paper describes the efforts to incorporate system-level digital design tools and state-of-the FPGA boards in the capstone design course sequence. This paper provides the details of two capstone projects in the areas of digital communications and image processing. This paper also details the challenges involved in using continually-evolving system-level design tools and the efforts made to reduce their learning times.

Introduction

ABET 2000 requires providing students with a significant hands-on design experience. Graduating electrical engineering students should have the ability to develop system-level designs for a variety of applications, implement these designs in functional hardware, and test the hardware in real-life operating conditions. To achieve such professional competence, students should be required to participate in a sequence of hardware design experiments and projects. These laboratory exercises aim at: a) sharpening students’ abilities to design complex digital circuits and systems, and to interface these designs to peripheral devices, b) exposes students to contemporary digital design tools, and c) provide students with lessons that can help them become long-life learners and successful professionals.

This paper describes the efforts to incorporate system-level digital design tools and state-of-the FPGA boards in the capstone design course sequence. This is part of the Electrical Engineering Department efforts to enhance the quality of upper division design courses through the introduction of computer-aided design and system-level design tools. These tools are vertically integrated with many of junior, upper-level, and capstone courses. The capstone design is a two- semester sequence courses. The cross-disciplinary capstone design projects emphasize the hardware/software implementation of algorithms, the design and use of intellectual property (IP) cores, and system-on-a-chip (SoC) concept.

The system-level software packages used include Matlab, Simulink, assortment of Matlab toolboxes and blocksets, Xilinx System Generator (SysGen), Xilinx embedded design kit (EDK), and Extreme DSP. Matlab blocksets provide commonly used design components needed to model the majority of digital control, DSP and digital communication systems. The Xilinx SysGen allows performing FPGA in the loop simulation with Simulink. A complete reconfigurable system can be developed and simulated in Simulink environment. The use of IP cores allow designers to concentrate on the overall system design and performance without having to spend time to verify the correctness or performance of the system’s components.

The FPGA boards include the Spartan 3 starter kit, the XUP-V2Pro, and the DO-ML403-EDK- ISE-PC4-US. The reconfigurable resources of these boards are used to implement the combinational and sequential logic needed to implement digital designs. It can also be used to

Mahmoud, W. (2007, June), Incorporating System Level Design Tools Into Upper Level Digital Design And Capstone Courses Paper presented at 2007 Annual Conference & Exposition, Honolulu, Hawaii. https://peer.asee.org/2735

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