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Integrating Systems On Chip In An Undergraduate Ece Curriculum

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2009 Annual Conference & Exposition


Austin, Texas

Publication Date

June 14, 2009

Start Date

June 14, 2009

End Date

June 17, 2009



Conference Session

NSF Grantees Poster Session

Page Count


Page Numbers

14.770.1 - 14.770.6



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Paper Authors


Ying Tang Rowan University

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Ying Tang is Associate Professor of Electrical and Computer Engineering at Rowan University, Glassboro, NJ. She received the B.S. and M.S. degrees from the Northeastern University, P. R. China, in 1996 and 1998, respectively, and Ph. D degree from New Jersey Institute of Technology, Newark, NJ, in 2001. Her research interests include operational research, discrete event systems, Petri nets applications, artificial intelligence, and hardware and software co-design.

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Linda Head Rowan University

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Linda M. Head is an Associate Professor of Electrical and Computer Engineering at Rowan University, Glassboro, New Jersey. She completed her Ph.D. studies in the Department of Electrical Engineering at the University of South Florida, Tampa in 1991. Her research interests include materials reliability for VLSI interconnects, rapid wafer-level test design, test structure development and noise characterization of materials and devices for integrated circuits

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Ravi Ramachandran Rowan University

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RAVI P. RAMACHANDRAN is a Professor at the Electrical and Computer Engineering at Rowan University, Glassboro, NJ. His research interests include digital signal processing, speech processing and pattern recognition. He teaches systems and control, signal processing, speech processing,
adaptive filters and complex variables at Rowan. He is a senior member of IEEE and member of ASEE

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Lawrence Chatman Camden County College

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Dr. Lawrence M. Chatman is an Associate Professor and Coordinator of Engineering Science and Technology at Camden County College in New Jersey where he teaches electrical, electronic and communication courses. He is a member of ASEE.

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NOTE: The first page of text has been automatically extracted and included below in lieu of an abstract

Integrating System-on-Chip in an Undergraduate ECE Curriculum

ABSTRACT System-on-Chip (SoC) is the major revolution taking place in the design of Integrated Circuits (IC). However, progress in this rapidly evolving area hinges critically on the availability of well-educated engineers able to bridge the architectural and physical gaps in SoC design. This work is an ambitious collaborative effort by the faculty of the Electrical and Computer Engineering (ECE) department at Rowan University and the Engineering Science (ES) department at Camden County College (CCC) to integrate System- on-Chip (SoC) concepts across the curricula. More specifically, a curricular prototype is under development that cuts across the artificial course boundaries and introduces SoC knowledge through vertically- integrated and problem-oriented laboratory experiments. Beginning with basic concepts, this approach immerses students in actual system-design projects through three specific engineering design flows (digital, analog, and signal processing) where experiences are formalized and encapsulated into reusable methods, libraries and tools. This paper focuses on the systematic and coherent experimental contents being conducted by students, their contributions to various SoC product designs, and how they fit seamlessly within the Rowan ECE and CCC ES curricula.


With the rapid progress of deep submicron technology, efforts in SoC have recently grown from the combination of digital core functions alone to the full integration of all digital and analog functions of a system. This paradigm shift has a significant impact on the skills needed by SoC architects. However, SoC education has not kept pace with this evolution, especially at the undergraduate level [2]. In fact, today’s electrical and computer engineering and computer science departments deliver either classical VLSI designers or computer specialists [1]. Therefore, there is a critical shortage of a new breed of SoC engineers that is capable of bridging the architectural and physical gaps in SoC design to meet the industry’s workforce demands in the years ahead [1]. As also indicated in [1], the best training for SoC architects must be oriented to problem solving through vertically integrated and multidisciplinary project components, evolving from analysis to open-ended product design at both the undergraduate and the graduate levels. As pointed out by the National Academy of Engineering report [3], “systems” have become the organizing principle for the way that engineering is viewed and engineering design is accomplished. SoC is much more “system” than “chip”, and involves aspects of the engineering curricula from basic circuit analysis to digital and analog hardware/software co-design to specialized signal processing procedures. If students understand that their courses are part of a flow that contributes to the design of a system rather than separate bodies of knowledge, they will be in a better position to appreciate the multidisciplinary nature of ECE and ES.

Motivated by these remarks, this project, as part of an NSF-CCLI grant, proposes an innovative approach comprising three fundamental strands of the curricula and vertically integrates SoC concepts with a focus on their contribution to SoC product design. As described below and shown schematically in Figure 1, this vertical integration of curricula: (1) Provides an Introductory Module during the Freshman year that presents an early overview of electrical and electronic systems; (2) Reinforces the system concept in laboratory experiments in Digital, Analog, and Signal Processing tracks through the sophomore and junior courses; and (3) Emphasizes System Design in a series of senior core and elective courses that call directly on project-oriented assignments that prioritize increasing complexity.

Tang, Y., & Head, L., & Ramachandran, R., & Chatman, L. (2009, June), Integrating Systems On Chip In An Undergraduate Ece Curriculum Paper presented at 2009 Annual Conference & Exposition, Austin, Texas. 10.18260/1-2--4574

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