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Integration Of Low Power Digital Circuitry Into Undergraduate Curricula

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Conference

2006 Annual Conference & Exposition

Location

Chicago, Illinois

Publication Date

June 18, 2006

Start Date

June 18, 2006

End Date

June 21, 2006

ISSN

2153-5965

Conference Session

Energy Curriculum Advancements

Tagged Division

Energy Conversion and Conservation

Page Count

13

Page Numbers

11.803.1 - 11.803.13

Permanent URL

https://peer.asee.org/500

Download Count

24

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Paper Authors

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Glenn Ellis Smith College

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Sarah Wodin-Schwartz Smith College

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Israel Koren University of Massachusetts-Amherst

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Baaba Andam Smith College

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C. Mani Krishna University of Massachusetts-Amherst

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C. Andras Moritz University of Massachusetts-Amherst

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Abstract
NOTE: The first page of text has been automatically extracted and included below in lieu of an abstract

Integration of Low-Power Digital Circuitry into Undergraduate Curricula

I. Introduction

Power-aware computing has become in recent years a significant area of research and development in both academia and industry1,2. Various techniques for reducing the temporal power and the long term energy consumption of embedded processors in general and mobile devices (e.g., cellular phones, PDAs and laptop computers) in particular, have been developed. Several new products whose main feature is lower power consumption have been introduced successfully into the marketplace. The techniques developed for achieving the reduced power and energy cover many phases of the computer system design including circuits, voltage scaling, micro-architectures and system software (i.e., operating systems and compilers).

Over the last ten years or so, power-aware computing has been transformed from a somewhat arcane and limited discipline to one of the most active areas in computer science and engineering. This trend has been fueled by the following: • Processors are becoming ever more power-hungry, and their power densities (watts/ cm2) are increasing rapidly. The power density of many modern processors exceeds that of a hotplate and that of the core of a nuclear reactor3. The problem of dissipating heat from a microprocessor is therefore becoming more acute. As feature sizes shrink, the fraction of energy lost to leakage will become significant. Leakage rises very rapidly with temperature: so running a processor hot will further increase power consumption, thereby setting up a positive feedback loop. Further, the processor failure rate increases with an increase in the operating temperature. • Battery-powered applications have proliferated. Battery technology has not advanced as rapidly as processor power consumption, and this limits the mean time between recharges. • The more obvious approaches to constraining power consumption, such as disk spindown and turning off the screen have already been implemented. More complex approaches are now being pursued for additional savings. • The aggregate power consumption of computers is no longer a negligible fraction of the total power consumption in the United States4. Approaches to reduce such power consumption can therefore be expected to make a measurable impact on the overall power consumed in the country.

There has been very little done in electrical engineering curricula to develop students’ skills and abilities to design efficient digital circuits. The Institute of Electrical and Electronics Engineers (IEEE) recommends that low-power digital circuit design be taught in the undergraduate curriculum for electrical and computer engineers5. Some institutions have begun to incorporate low power digital circuits into the electrical/ computer engineering curriculum, but their methods of implementation have added to the course load of the undergraduates and are all optional. King Fahd University of Petroleum and Minerals in Saudi Arabia has developed a senior level course,

Ellis, G., & Wodin-Schwartz, S., & Koren, I., & Andam, B., & Krishna, C. M., & Moritz, C. A. (2006, June), Integration Of Low Power Digital Circuitry Into Undergraduate Curricula Paper presented at 2006 Annual Conference & Exposition, Chicago, Illinois. https://peer.asee.org/500

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