Introducing Laboratories with Soft Processor Cores Using FPGAs into the Computer Engineering Curriculum

David Henry Hoe

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Conference: 2012 ASEE Annual Conference & Exposition
Location: San Antonio, Texas
Publication Date: June 10, 2012
Start Date: June 10, 2012
End Date: June 13, 2012
ISSN: 2153-5965
Conference Session: Electrical and Computer Poster Session
Tagged Division: Electrical and Computer
Page Count: 9
Page Numbers: 25.844.1 - 25.844.9
DOI: 10.18260/1-2--21601
Permanent URL: https://peer.asee.org/21601
Download Count: 657

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David Henry Hoe University of Texas, Tyler

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David Hoe received his Ph.D. in electrical engineering from the University of Toronto. He held a position as a Staff Engineer at the General Electric Corporate Research and Development Center for five years prior to assuming his current position as an Assistant Professor in the Electrical Engineering Department at the University of Texas, Tyler, in 2008.

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Abstract

Introducing Laboratories with Soft Processor Cores Using FPGAs into the Computer Engineering CurriculumContinued advances in semiconductor technology have enabled Field Programmable Gate Arrays(FPGAs) to implement soft processor cores. These configurable microprocessors are completelyspecified by a High-level Descriptor Language (HDL). While not as fast or low power as fullcustom integrated circuit designs, they offer more flexibility as they can be optimized for aparticular application. Soft processor cores are becoming an important component in the trendtowards designing Systems-on-a-Programmable-Chip (SoPC). Since it is important to train ourstudents in the latest technology used by practicing engineers in industry, soft processor designhas been introduced into two courses within the Computer Engineering curriculum at theUniversity of ________. This paper will describe the development of the labs and the results oftheir implementation as well as plans to further develop and expand the soft processor labs.The FPGA Design and Computer Architecture courses currently exist as senior electives in thecomputer engineering track as well as graduate courses at the MSEE level at our university. Thesoft processor core laboratory was introduced into the FPGA Design classes at both the graduateand undergraduate level this past spring semester. The labs for that class introduce the students tothe basics of VHDL coding and have them implement logic blocks such as counters, adders, andmultipliers. Three labs were added to the course with the objective of introducing the students tosoft processor core design so that they understand the advantages compared to using a fixedmicrocontroller. In addition, the goal is to give the students practical experience using the toolsto implement a small design project using the soft processor and the necessary support logic onan FPGA. Xilinx’s PicoBlaze microcontroller, an 8-bit processor that is fully specified in VHDL,was chosen as several tools exist for design and debug of the processor and the processor issimple enough that students can learn its architecture and how to program it using assemblylanguage within the context of the course. To keep the level of complexity manageable for anintroductory course, the students are given a detailed tutorial outlining the steps needed toassemble and compile the ROM code to control the microcontroller and instructions on how tointerface supporting logic with the processor. The graduate students were given a course projectto design a stop-watch using the soft processor. They had to add hardware interfaces to switchesand an LED display, and learn how to write an Interrupt Service Routine (ISR). Based on theproject reports, oral interviews, and test scores, this initial effort was deemed to have met itsobjectives.The multiprocessor system, an important development in processor design, was introduced intothe Computer Architecture class a year ago. By taking advantage of instruction level parallelismby having many simpler processor cores operating at lower frequency than a uniprocessor, amultiprocessor system is able to overcome the limits on processor efficiency due to themaximum frequency constraint of the “power wall.” A decision this past summer was made tointroduce a multiprocessor lab into the class. The objective was to give the students someunderstanding of both the hardware and software issues associated with multiprocessor design.Xilinx’s PicoBlaze processor was used again as the processor to be arrayed within the FPGA.The challenge was to implement the hardware interface in VHDL and the software code inassembly language to have the processors communicate effectively with each other. This paperwill detail the mailbox (FIFO) approach used in the lab. The effectiveness of this lab wasevaluated through tracking of student test scores and survey of student attitudes towards the lab.Based on positive results, plans are underway to expand the multiprocessor lab in upcomingcourse offerings. Details regarding the development of several more multiprocessor labs,including the use of shared memory and the implementation of a Finite Impulse Response (FIR)filter using an array of PicoBlaze processors, will also be discussed in this paper. Theeffectiveness of these labs will be evaluated using surveys to track student learning attitudes,faculty observation, quality of lab reports, and correlation with test scores.

Citation
Format

Hoe, D. H. (2012, June), Introducing Laboratories with Soft Processor Cores Using FPGAs into the Computer Engineering Curriculum Paper presented at 2012 ASEE Annual Conference & Exposition, San Antonio, Texas. 10.18260/1-2--21601

TY  - CPAPER
AB  -        Introducing Laboratories with Soft Processor Cores Using FPGAs                 into the Computer Engineering CurriculumContinued advances in semiconductor technology have enabled Field Programmable Gate Arrays(FPGAs) to implement soft processor cores. These configurable microprocessors are completelyspecified by a High-level Descriptor Language (HDL). While not as fast or low power as fullcustom integrated circuit designs, they offer more flexibility as they can be optimized for aparticular application. Soft processor cores are becoming an important component in the trendtowards designing Systems-on-a-Programmable-Chip (SoPC). Since it is important to train ourstudents in the latest technology used by practicing engineers in industry, soft processor designhas been introduced into two courses within the Computer Engineering curriculum at theUniversity of ________. This paper will describe the development of the labs and the results oftheir implementation as well as plans to further develop and expand the soft processor labs.The FPGA Design and Computer Architecture courses currently exist as senior electives in thecomputer engineering track as well as graduate courses at the MSEE level at our university. Thesoft processor core laboratory was introduced into the FPGA Design classes at both the graduateand undergraduate level this past spring semester. The labs for that class introduce the students tothe basics of VHDL coding and have them implement logic blocks such as counters, adders, andmultipliers. Three labs were added to the course with the objective of introducing the students tosoft processor core design so that they understand the advantages compared to using a fixedmicrocontroller. In addition, the goal is to give the students practical experience using the toolsto implement a small design project using the soft processor and the necessary support logic onan FPGA. Xilinx’s PicoBlaze microcontroller, an 8-bit processor that is fully specified in VHDL,was chosen as several tools exist for design and debug of the processor and the processor issimple enough that students can learn its architecture and how to program it using assemblylanguage within the context of the course. To keep the level of complexity manageable for anintroductory course, the students are given a detailed tutorial outlining the steps needed toassemble and compile the ROM code to control the microcontroller and instructions on how tointerface supporting logic with the processor. The graduate students were given a course projectto design a stop-watch using the soft processor. They had to add hardware interfaces to switchesand an LED display, and learn how to write an Interrupt Service Routine (ISR). Based on theproject reports, oral interviews, and test scores, this initial effort was deemed to have met itsobjectives.The multiprocessor system, an important development in processor design, was introduced intothe Computer Architecture class a year ago. By taking advantage of instruction level parallelismby having many simpler processor cores operating at lower frequency than a uniprocessor, amultiprocessor system is able to overcome the limits on processor efficiency due to themaximum frequency constraint of the “power wall.” A decision this past summer was made tointroduce a multiprocessor lab into the class. The objective was to give the students someunderstanding of both the hardware and software issues associated with multiprocessor design.Xilinx’s PicoBlaze processor was used again as the processor to be arrayed within the FPGA.The challenge was to implement the hardware interface in VHDL and the software code inassembly language to have the processors communicate effectively with each other. This paperwill detail the mailbox (FIFO) approach used in the lab. The effectiveness of this lab wasevaluated through tracking of student test scores and survey of student attitudes towards the lab.Based on positive results, plans are underway to expand the multiprocessor lab in upcomingcourse offerings. Details regarding the development of several more multiprocessor labs,including the use of shared memory and the implementation of a Finite Impulse Response (FIR)filter using an array of PicoBlaze processors, will also be discussed in this paper. Theeffectiveness of these labs will be evaluated using surveys to track student learning attitudes,faculty observation, quality of lab reports, and correlation with test scores.
AU  - David Henry Hoe
CY  - San Antonio, Texas
DA  - 2012/06/10
PB  - ASEE Conferences
TI  - Introducing Laboratories with Soft Processor Cores Using FPGAs into the Computer Engineering Curriculum 
UR  - https://peer.asee.org/21601
DO  - 10.18260/1-2--21601
ER  -