Introducing Nanoelectronics into the Electrical Engineering Curriculum

David H Hoe

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Conference: 2013 ASEE Annual Conference & Exposition
Location: Atlanta, Georgia
Publication Date: June 23, 2013
Start Date: June 23, 2013
End Date: June 26, 2013
ISSN: 2153-5965
Conference Session: Electrical and Computer Engineering (ECE) Poster Session
Tagged Division: Electrical and Computer
Page Count: 15
Page Numbers: 23.821.1 - 23.821.15
DOI: 10.18260/1-2--19835
Permanent URL: https://peer.asee.org/19835
Download Count: 696

Paper Authors

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David H Hoe University of Texas, Tyler

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Dr. David Hoe is an Assistant Professor in the Electrical Engineering department at the University of Texas at Tyler since 2008.

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Abstract

Introducing Nanoelectronics into the Electrical Engineering CurriculumAs the scaling of Very Large Scale Integration (VLSI) technology continues to follow Moore’sLaw, transistors can now be fabricated with feature sizes around 20 nm. This has allowed therealization of integrated circuits (ICs) with remarkable density and functionality, such as multi-core processors with well over a billion transistors. However, conventional silicon fabricationtechnology will reach its limits in the next few years. Radically new devices that are engineeredat the nanoscale are poised to replace silicon technology and allow continued increases in deviceintegration density along with the resultant increases in computing power. Hence, it is essentialthat universities educate electrical engineering students in these new nanotechnologies.Engineering programs that have introduced nanotechnology into their curriculum typically addmaterial into core classes or have added a separate set of nanotechnology courses [1, 2].Increasing the number of courses can be a challenge for colleges with limited resources andfaculty and it is not easy to make significant changes to the curriculum all in one step. This paperlooks at an alternative that is being introduced at the University of _______. The goal is tointroduce nanotechnology into select courses while minimizing changes to the curriculum forease of adoption. The proposed solution is to introduce nanoscale design concepts into existingclasses which teach microelectronic-related topics and where nanotechnology will revolutionizethe way these circuits are built in the near future. An advantage of this approach is that thestudents have a prior context to build upon. They can see how state-of-the art microelectroniccircuits are currently designed while comparing and contrasting it with the paradigmatic shiftoffered by nanoelectronic devices. This juxtaposition of technologies is appropriate since anumber of proposed nanoelectronic circuits are built upon similar principles and topologies usedin current microelectronic technologies and a feasible near-term solution is to manufacturehybrid nano-microelectronic circuits.This paper will focus on a VLSI Design course where we are introducing a series ofnanoelectronic learning modules. The primary features of these modules are the use of activelearning techniques that foster peer collaboration with in-class exercises combined with readingsfrom the primary literature. The modules cover nanometer scale fabrication and design issueswith current silicon technology as well as two of the most promising near-term nanotechnologiesfor implementing high-speed digital logic, carbon nanotubes and silicon nanowires [3-4]. Somerecent research on multi-valued logic and pass-transistor logic design using carbon nanotubetransistors are discussed [5]. Recent studies on integrating conventional silicon technology withnanotechnology as a near-term solution are also covered [6]. The assessment of this approachconsists of three parts. First, we are utilizing surveys to obtain student self-assessment of theirattitudes and motivation. Second, we are developing concept inventory tests to measure gains inthe conceptual knowledge of the students. Third, student understanding is measured on test andexam scores and compared against material not taught with the learning modules. Initial resultsindicate students are motivated by reading from the primary literature and appreciate the use ofin-class peer interaction on the learning modules. The paper will provide complete statistics andanalysis from the VLSI course from this current semester and discuss plans to utilize thisapproach in two additional courses that cover reconfigurable computing and analog IC design inthe coming year.References[1] Pai, D. et al., 2006. Introducing Nanotechnology into Traditional Engineering Curricula, 9th International Conference on Engineering Education, Session T1D, pp. 11-16.[2] Al-Haik, M., 2010. Introducing Nanotechnology to Mechanical and Civil Engineering Students Through Materials Science Courses, Journal of Nano Education, vol. 2, pp. 13–26.[3] Appenzeller, J., 2008. Carbon Nanotubes for High-Performance Electronics—Progress and Prospect, Proceedings of the IEEE, vol. 96, no. 2, pp. 201-211.[4] Wang, D, Sheriff, B. A., McAlpine, M., and Heath, J. R., 2008. Development of Ultra-High Density Silicon Nanowire Arrays for Electronics Applications, Nano Res, vol. 1, pp. 9-21.[5] Lin, S., Kim, Y.-B., and Lombardi, F., 2011. CNTFET-Based Design of Ternary Logic Gates and Arithmetic Circuits, IEEE Transactions on Nanotechnology, vol. 10, no. 2, pp. 217-225.[6] Snider, G. S. and Williams, R. S., 2007. Nano/CMOS architectures using a field-programmable nanowire interconnect, Nanotechnology, vol. 18, pp. 1-11.

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Hoe, D. H. (2013, June), Introducing Nanoelectronics into the Electrical Engineering Curriculum Paper presented at 2013 ASEE Annual Conference & Exposition, Atlanta, Georgia. 10.18260/1-2--19835

TY - CPAPER
AB - Introducing Nanoelectronics into the Electrical Engineering CurriculumAs the scaling of Very Large Scale Integration (VLSI) technology continues to follow Moore’sLaw, transistors can now be fabricated with feature sizes around 20 nm. This has allowed therealization of integrated circuits (ICs) with remarkable density and functionality, such as multi-core processors with well over a billion transistors. However, conventional silicon fabricationtechnology will reach its limits in the next few years. Radically new devices that are engineeredat the nanoscale are poised to replace silicon technology and allow continued increases in deviceintegration density along with the resultant increases in computing power. Hence, it is essentialthat universities educate electrical engineering students in these new nanotechnologies.Engineering programs that have introduced nanotechnology into their curriculum typically addmaterial into core classes or have added a separate set of nanotechnology courses [1, 2].Increasing the number of courses can be a challenge for colleges with limited resources andfaculty and it is not easy to make significant changes to the curriculum all in one step. This paperlooks at an alternative that is being introduced at the University of _______. The goal is tointroduce nanotechnology into select courses while minimizing changes to the curriculum forease of adoption. The proposed solution is to introduce nanoscale design concepts into existingclasses which teach microelectronic-related topics and where nanotechnology will revolutionizethe way these circuits are built in the near future. An advantage of this approach is that thestudents have a prior context to build upon. They can see how state-of-the art microelectroniccircuits are currently designed while comparing and contrasting it with the paradigmatic shiftoffered by nanoelectronic devices. This juxtaposition of technologies is appropriate since anumber of proposed nanoelectronic circuits are built upon similar principles and topologies usedin current microelectronic technologies and a feasible near-term solution is to manufacturehybrid nano-microelectronic circuits.This paper will focus on a VLSI Design course where we are introducing a series ofnanoelectronic learning modules. The primary features of these modules are the use of activelearning techniques that foster peer collaboration with in-class exercises combined with readingsfrom the primary literature. The modules cover nanometer scale fabrication and design issueswith current silicon technology as well as two of the most promising near-term nanotechnologiesfor implementing high-speed digital logic, carbon nanotubes and silicon nanowires [3-4]. Somerecent research on multi-valued logic and pass-transistor logic design using carbon nanotubetransistors are discussed [5]. Recent studies on integrating conventional silicon technology withnanotechnology as a near-term solution are also covered [6]. The assessment of this approachconsists of three parts. First, we are utilizing surveys to obtain student self-assessment of theirattitudes and motivation. Second, we are developing concept inventory tests to measure gains inthe conceptual knowledge of the students. Third, student understanding is measured on test andexam scores and compared against material not taught with the learning modules. Initial resultsindicate students are motivated by reading from the primary literature and appreciate the use ofin-class peer interaction on the learning modules. The paper will provide complete statistics andanalysis from the VLSI course from this current semester and discuss plans to utilize thisapproach in two additional courses that cover reconfigurable computing and analog IC design inthe coming year.References[1] Pai, D. et al., 2006. Introducing Nanotechnology into Traditional Engineering Curricula, 9th International Conference on Engineering Education, Session T1D, pp. 11-16.[2] Al-Haik, M., 2010. Introducing Nanotechnology to Mechanical and Civil Engineering Students Through Materials Science Courses, Journal of Nano Education, vol. 2, pp. 13–26.[3] Appenzeller, J., 2008. Carbon Nanotubes for High-Performance Electronics—Progress and Prospect, Proceedings of the IEEE, vol. 96, no. 2, pp. 201-211.[4] Wang, D, Sheriff, B. A., McAlpine, M., and Heath, J. R., 2008. Development of Ultra-High Density Silicon Nanowire Arrays for Electronics Applications, Nano Res, vol. 1, pp. 9-21.[5] Lin, S., Kim, Y.-B., and Lombardi, F., 2011. CNTFET-Based Design of Ternary Logic Gates and Arithmetic Circuits, IEEE Transactions on Nanotechnology, vol. 10, no. 2, pp. 217-225.[6] Snider, G. S. and Williams, R. S., 2007. Nano/CMOS architectures using a field-programmable nanowire interconnect, Nanotechnology, vol. 18, pp. 1-11.
AU - David H Hoe
CY - Atlanta, Georgia
DA - 2013/06/23
PB - ASEE Conferences
TI - Introducing Nanoelectronics into the Electrical Engineering Curriculum
UR - https://peer.asee.org/19835
DO - 10.18260/1-2--19835
ER -