Haberly, J., & Hack, I. (2001, June), Low Cost FPGA Development System For Teaching Advanced Digital Circuits  Paper presented at 2001 Annual Conference, Albuquerque, New Mexico. 10.18260/1-2--9526

\bibitem{asee_peer_9526}
  Haberly, J., \& Hack, I. (2001, June), \emph{Low Cost FPGA Development System For Teaching Advanced Digital Circuits}
  Paper presented at 2001 Annual Conference, Albuquerque, New Mexico.
  10.18260/1-2--9526

James Haberly and Iskandar Hack.  "Low Cost FPGA Development System For Teaching Advanced Digital Circuits".  2001 Annual Conference, Albuquerque, New Mexico, 2001, June.  ASEE Conferences, 2001.  https://peer.asee.org/9526 Internet.  19 Dec, 2024

\bibitem{asee_peer_9526}
  James Haberly and Iskandar Hack.
  "Low Cost FPGA Development System For Teaching Advanced Digital Circuits".
  \emph{2001 Annual Conference, Albuquerque, New Mexico, 2001, June}.
  ASEE Conferences, 2001.
  https://peer.asee.org/9526 Internet.  19 Dec, 2024

@INPROCEEDINGS{asee_peer_9526
author = "James Haberly and Iskandar Hack"
title = "Low Cost FPGA Development System For Teaching Advanced Digital Circuits"
booktitle = "2001 Annual Conference"
year = "2001"
month = "June"
address = "Albuquerque, New Mexico"
publisher = "ASEE Conferences"
note = {https://peer.asee.org/9526}
number = {10.18260/1-2--9526}
}

TY  - CPAPER
AB  - This paper covers the development of student development system to use with the Altera Max+ PLUS software for teaching Field Programmable Gate Arrays (FPGA’s) and Complex Programmable Logic Devices (CPLD’s). This software is available free of charge from Altera directly for students to download for use in at home or can be installed via an educational license in any university laboratory. The student version of the software includes a schematic editor and design entry, waveform editor for design entry, Altera Hardware Description Language design (AHDL) Entry, and the industry standard VHDL (VHSIC (Very High Speed Integrated Circuits) Hardware Description Language) design entry. Thus this system can be used to teach all of the major design techniques used in modern digital circuit design. The hardware portion of the development system includes an in-circuit programmable Altera CPLD on a printed circuit board (PCB) with adequate space on the breadboard area for students to development their own projects. The programming is done using a standard PC parallel port; thus there is no need for any additional programming hardware. Also mounted on the board are DB-25 and DB-9 connectors for implementing serial communication laboratories. The current system is using a standard student breadboard that is mounted onto the development board, and jumpers are used to connect the pins from the CPLD to the breadboard area or the serial connectors. There is also a laboratory manual, containing thirteen laboratory assignments and a list of final projects, that accompanies the development system designed to take a second semester Electrical Engineering Technology student from a basic introduction to Computer Aided Engineering (CAE) to a final project using the Altera Hardware Descriptive Language (AHDL), along with a short introduction to VHDL. The manual stresses basic design techniques along with simulation analysis prior to implementing the designs on the development hardware. The board has been used at Indiana Purdue University at Fort Wayne for the last three years, and the laboratory manual has just been developed.
AU  - James Haberly
AU  - Iskandar Hack
CY  - Albuquerque, New Mexico
DA  - 2001/06/24
PB  - ASEE Conferences
TI  - Low Cost FPGA Development System For Teaching Advanced Digital Circuits
UR  - https://peer.asee.org/9526
DO  - 10.18260/1-2--9526
ER  -