Minaie, A., & Nielson, E. (2018, June), Modeling a Perceptron Neuron Using Verilog Developed Floating-Point Numbering System and Modules for Hardware Synthesis  Paper presented at 2018 ASEE Annual Conference & Exposition , Salt Lake City, Utah. 10.18260/1-2--30815

\bibitem{asee_peer_30815}
  Minaie, A., \& Nielson, E. (2018, June), \emph{Modeling a Perceptron Neuron Using Verilog Developed Floating-Point Numbering System and Modules for Hardware Synthesis}
  Paper presented at 2018 ASEE Annual Conference \& Exposition , Salt Lake City, Utah.
  10.18260/1-2--30815

Afsaneh Minaie and Ephraim Nielson.  "Modeling a Perceptron Neuron Using Verilog Developed Floating-Point Numbering System and Modules for Hardware Synthesis".  2018 ASEE Annual Conference & Exposition , Salt Lake City, Utah, 2018, June.  ASEE Conferences, 2018.  https://peer.asee.org/30815 Internet.  22 Apr, 2024

\bibitem{asee_peer_30815}
  Afsaneh Minaie and Ephraim Nielson.
  "Modeling a Perceptron Neuron Using Verilog Developed Floating-Point Numbering System and Modules for Hardware Synthesis".
  \emph{2018 ASEE Annual Conference \& Exposition , Salt Lake City, Utah, 2018, June}.
  ASEE Conferences, 2018.
  https://peer.asee.org/30815 Internet.  22 Apr, 2024

@INPROCEEDINGS{asee_peer_30815
author = "Afsaneh Minaie and Ephraim Nielson"
title = "Modeling a Perceptron Neuron Using Verilog Developed Floating-Point Numbering System and Modules for Hardware Synthesis"
booktitle = "2018 ASEE Annual Conference \& Exposition "
year = "2018"
month = "June"
address = "Salt Lake City, Utah"
publisher = "ASEE Conferences"
note = {https://peer.asee.org/30815}
number = {10.18260/1-2--30815}
}

TY  - CPAPER
AB  - Implementing a Perceptron Neural Network on DE2-115 FPGA using IEEE 754 Single-Precision Designed Modules in Verilog 
	
	
	

Abstract

Capstone courses play a crucial role in Computer Engineering curricula.  The principle purpose of a Capstone project course is to offer a summative opportunity for graduating senior engineering students to apply their professional skills and knowledge in a single experience and prepare them for work in industry.   Like many engineering programs, students at XXX XXXX XXXXXXXX complete their requirements for graduation with a semester long capstone design project course.  The intention of this course is to apply competencies gained during their first three years toward the solution of a design problem.  Our senior design course is structured as a collection of independent student projects. As our students are required to design, build, and troubleshoot a fully functional project, they find this course both challenging and rewarding. 

The field of computational intelligence is quickly becoming important in all areas of technology. Neural networks, a subset of computational intelligence are the most implemented types of intelligent computation systems used in many types of machine learning and data mining applications from image recognition and classification, to search engine optimization, to data analysis. The future of technology seems to point towards the continual development and application of neural networks.  The remarkable growth in computational intelligence has given rise to a demand for engineers and computer scientists with experience in this field.  This paper presents a project in the field of neural networks which was developed as part of a senior design project course.

Key to the importance of hardware development for neural network implementation is the value of process parallelization. This project consists of the parallelization of computational process used to form a perceptron neural network. Requirements for this include the use of IEEE 754 single-precision floating-point binary number system for all component development, Altera DE2-115 FPGA implementation, Altera Quartus Prime Verilog code development, and test bench design used for project validation, verification, and testing of modules by Altera’s ModelSim software. 






AU  - Afsaneh Minaie
AU  - Ephraim Nielson
CY  - Salt Lake City, Utah
DA  - 2018/06/23
PB  - ASEE Conferences
TI  - Modeling a Perceptron Neuron Using Verilog Developed Floating-Point Numbering System and Modules for Hardware Synthesis
UR  - https://peer.asee.org/30815
DO  - 10.18260/1-2--30815
ER  -