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Multi-core Processor Learning Using a Simulator and Pin Tools

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2019 ASEE Annual Conference & Exposition


Tampa, Florida

Publication Date

June 15, 2019

Start Date

June 15, 2019

End Date

June 19, 2019

Conference Session

Technical Session 10: Simulation and Modeling

Tagged Division

Computers in Education

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Paper Authors


Yul Chu University of Texas, Rio Grande Valley

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Dr. Yul Chu is an Associate Professor in the Department of Electrical Engineering at the University of Texas Rio Grande Valley. He received his Ph.D. in Electrical and Computer Engineering from the University of British Columbia, Canada in 2001 and MS in Electrical engineering from Washington State University in 1995. His current research interests lie in the area of low-power embedded systems, high-performance computing, parallel processing, cluster and high-available architectures, computer networking, digital system design, etc.

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This paper describes the study of computer architecture labs, which can provide students to explore how the multi-core processor works by implementing a multi-core cache architecture. The pedagogical approach for this paper is based on the Kolb experiential learning style. This paper recommends using a simple simulator (which author has developed) and Pin Tool (which is an Intel open-source to make a trace file for benchmark programs). The simple simulator is to implement any detailed characteristics for a cache scheme, such as various cache operations, average memory access time, coherence protocol, # of bus traffics, power consumption, etc. The major steps for the simulator are as follows: 1) Getting input parameters from the command line; 2) Fetching instruction/data from a trace file; 3) Implementing cache hits /miss for ‘Single-Core’; 4) Implementing cache hits /miss based on ‘Cache-Coherence’; and 5) Providing output results. In addition, the Intel open-source PIN Tool is to collect trace files. The trace files are inserted into the cache simulator to get the outputs, which will be used for the system performance analyses. This paper proposes Kolb learning styles using three class modules in sequence. Those are 1) Module 1: teaching approach (e.g., 7 or 8 lectures) to learn basic concepts and operations for the multi-core cache memory operations; 2) Module 2: instructional technologies regarding how to run the simulator and PIN Tool to implement a cache memory architecture; and 3) Module 3: institutional strategies to support how to design and implement a multi-core cache architecture successfully. The outcomes will be rated by three factors, such as measurement of three modules, student feedback, and career development status. Firstly, the measurement of three basic modules are as follows: 1) Module 1 measurement: one (or two) exam(s) and teaching evaluation for the several lectures; 2) Module 2 measurement: report grading for each lab and a design project including demonstration; and 3) Module 3 measurement: grading for final reports, presentations, and demonstrations. Secondly, the paper provides several questions to get honest feedback and comments from students regarding how they comprehend a multi-core processor learning by using the simple simulator and PIN Tools. Then, this paper analyzes those feedbacks to enhance the contents of three modules as a future work. Lastly, for career development status, this paper suggests collecting the statistics for the internships and permanent job achievements for seniors and graduate students. To enhance the effectiveness of the outcomes, this paper discusses the module materials and education methods for the future Kolb’s learning styles based on the assessment results for the above three factors.

Chu, Y. (2019, June), Multi-core Processor Learning Using a Simulator and Pin Tools Paper presented at 2019 ASEE Annual Conference & Exposition , Tampa, Florida. 10.18260/1-2--33125

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