Albuquerque, New Mexico
June 24, 2001
June 24, 2001
June 27, 2001
6.810.1 - 6.810.11
Process Development for an Undergraduate Microchip Fabrication Facility†
Christopher T. Timmons, David T. Gray, and Robert W. Hendricks Virginia Polytechnic Institute and State University
We have built a microchip fabrication facility for teaching the elements of semiconductor processing to a multidisciplinary group of approximately 500 students per year from all areas of engineering, science, and even the humanities. In order to meet our pedagogical objectives of introducing microchip fabrication to introductory students, we have developed a four-mask, nine- step nMOS process using 100 µm rules for use with 4-inch wafers that can be completed by students working in teams of four in six two-hour laboratory periods. Our masksets and the processes used were developed in less than a year, primarily by senior level students in materials, chemical, and electrical engineering.
Virginia Polytechnic Institute and State University, under the auspices of the Virginia Microelectronics Consortium (VMEC), the Bradley Department of Electrical and Computer Engineering, and the Materials Science and Engineering Department, has developed an 1,800 ft 2 Class 10,000 cleanroom for teaching the elements of the microchip fabrication process to a multidisciplinary cohort of students from all areas of engineering, science, and even the humanities. The estimated throughput is approximately 500 students per year (about 170 students per semester). The development of our Class 10,000 cleanroom and the operation of our facility are described elsewhere.1
The process we have developed follows a manufacturing scheme to fabricate simple devices and simple testable circuits. We design our photolithography masks in AutoCadTM and print them on standard transparencies using a high-resolution Alps MicrodryTM printer. This simple mask design and generation procedure allows process flexibility at minimum cost—a complete maskset costs less than a dollar. Further, such simplicity will allow advanced students to design, fabricate, and test wafers using their own masksets. For our introductory class, the mask design includes resistors, p-n junctions, nMOS transistors, and simple circuits, as well as regions for device characterization and analysis. During the processing, students visually inspect and electrically test their wafers to insure the quality of processing. Students can test their wafers and devices using software written in LabView, which permits standard and custom tests. Typically, we measure the sheet resistivity after each processing step and we measure I–V curves for each device. The
† A version of this manuscript with gray-scale images suitable for color vision-impaired readers may be found at http://www.mse.vt.edu/faculty/hendricks/publications/publications.html.
Proceedings of the 2001 American Society for Engineering Education Annual Conference & Exposition Copyright © 2001, American Society for Engineering Education
Gray, D., & Timmons, C., & Hendricks, R. (2001, June), Process Development For An Undergraduate Microchip Fabrication Facility Paper presented at 2001 Annual Conference, Albuquerque, New Mexico. https://peer.asee.org/9681
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