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Real-time System Implementation for Video Processing

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Conference

2016 ASEE Annual Conference & Exposition

Location

New Orleans, Louisiana

Publication Date

June 26, 2016

Start Date

June 26, 2016

End Date

August 28, 2016

ISBN

978-0-692-68565-5

ISSN

2153-5965

Conference Session

Integrating Systems Engineering into the Capstone Project

Tagged Divisions

Systems Engineering and Multidisciplinary Engineering

Page Count

9

DOI

10.18260/p.26042

Permanent URL

https://peer.asee.org/26042

Download Count

1066

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Paper Authors

biography

Wagdy H Mahmoud University of the District of Columbia

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Wagdy H. Mahmoud is an Associate Professor of electrical engineering at the Electrical Engineering Department at UDC. Mahmoud is actively involved in research in the areas of reconfigurable logic, hardware/software co-design of a system on a chip using reconfigurable logic, application-specific integrated circuits (ASIC), digital logic design, image compressions, digital signal processing, computer architecture, embedded systems, system on a chip, and renewable energy.

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biography

Sasan Haghani University of the District of Columbia

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Sasan Haghani, Ph.D., is an Associate Professor of Electrical and Computer Engineering at the University of the District of Columbia. His research interests include the application of wireless sensor networks in biomedical and environmental domains and performance analysis of communication systems over fading channels.

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Roussel Kamaha

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Abstract

Real time image and video processing is a requirement in many computer vision applications, e.g. video surveillance, pattern recognition, compression, object identification and tracking, feature extraction, traffic management and medical imaging. Edge detection is the most common preprocessing step in the implementation of the algorithms of video and image processing applications. The Canny edge detector is one of the most widely-used edge detection algorithms due to its superior performance. Modern Field Programmable Gate Arrays (FPGAs) with high logic capacity, embedded multipliers and microprocessor are becoming the platform of choice for the hardware/software co-design implementations of computational-intensive applications such as image and video-processing systems The ever-increasing complexity of digital systems including real-time video processing systems have compelled the Electronic System Level (ESL) community to switch over from Register Transfer Level (RTL) languages such as VHDL and Verilog to higher abstraction level languages such as C/C++ in order to reduce the overall design time and improve the productivity of system-level designers. Recent improvements in High Level Synthesis (HLS) tools has allowed for the development of highly-optimized video processing systems. This paper details the results of a capstone design project to develop a real-time hardware/software video processing system to implement Canny edge detection algorithm on a Zynq FPGA platform. The HSL tool, part of the Xilinx Vivado design environment, was used to develop the hardware accelerator for the algorithm. The paper will provide an overview of Canny edge detection algorithms, the details of the hardware/software system to detect edges in a real-time 1080p full HD input video stream, and the overall performance of the designed system. The paper also details the process used to help students complete such a complex project and their contributions on the professional development of students. Keywords - High Level Synthesis, Canny edge detection, real-time video processing systems.

Mahmoud, W. H., & Haghani, S., & Kamaha, R. (2016, June), Real-time System Implementation for Video Processing Paper presented at 2016 ASEE Annual Conference & Exposition, New Orleans, Louisiana. 10.18260/p.26042

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