Hussein, R., & Maloney, R. C., & Rodriguez-Gil, L., & Beroz, J. A., & Orduna, P. (2023, June), RHL-BEADLE: Bringing Equitable Access to Digital Logic Design in Engineering Education  Paper presented at 2023 ASEE Annual Conference & Exposition, Baltimore , Maryland. 10.18260/1-2--44147

\bibitem{asee_peer_44147}
  Hussein, R., \& Maloney, R. C., \& Rodriguez-Gil, L., \& Beroz, J. A., \& Orduna, P. (2023, June), \emph{RHL-BEADLE: Bringing Equitable Access to Digital Logic Design in Engineering Education}
  Paper presented at 2023 ASEE Annual Conference \& Exposition, Baltimore , Maryland.
  10.18260/1-2--44147

Rania Hussein, Riley Connor Maloney, Luis Rodriguez-Gil, Jon Ander Beroz, and Pablo Orduna.  "RHL-BEADLE: Bringing Equitable Access to Digital Logic Design in Engineering Education".  2023 ASEE Annual Conference & Exposition, Baltimore , Maryland, 2023, June.  ASEE Conferences, 2023.  https://peer.asee.org/44147 Internet.  27 Dec, 2024

\bibitem{asee_peer_44147}
  Rania Hussein, Riley Connor Maloney, Luis Rodriguez-Gil, Jon Ander Beroz, and Pablo Orduna.
  "RHL-BEADLE: Bringing Equitable Access to Digital Logic Design in Engineering Education".
  \emph{2023 ASEE Annual Conference \& Exposition, Baltimore , Maryland, 2023, June}.
  ASEE Conferences, 2023.
  https://peer.asee.org/44147 Internet.  27 Dec, 2024

@INPROCEEDINGS{asee_peer_44147
author = "Rania Hussein, Riley Connor Maloney, Luis Rodriguez-Gil, Jon Ander Beroz, and Pablo Orduna"
title = "RHL-BEADLE: Bringing Equitable Access to Digital Logic Design in Engineering Education"
booktitle = "2023 ASEE Annual Conference \& Exposition"
year = "2023"
month = "June"
address = "Baltimore , Maryland"
publisher = "ASEE Conferences"
note = {https://peer.asee.org/44147}
number = {10.18260/1-2--44147}
}

TY  - CPAPER
AB  - The vast scope of digital design and the cost associated with purchasing and maintaining specialized lab equipment can pose a significant obstacle for pre-college students. This challenge is particularly significant for students from low-income and underrepresented minority backgrounds who often begin their higher education journey in community college programs with limited funding and access to engineering hardware. BEADLE, a project designed to promote equity in access to educational technologies, seeks to address this issue by providing an affordable platform that allows students to remotely access industry-grade hardware to learn and develop their skills in digital design as a step towards pursuing advanced digital design coursework in a university setting. The success of an advanced digital design course delivered using a remote Field Programmable Gate Arrays (FPGA) lab inspired the creation of an introductory digital logic curriculum for 2-year community college and high school students. The BEADLE curriculum is designed to prepare students for a junior-level course in computer engineering at a 4-year university, where digital logic is typically taken during the first two years. To evaluate the curriculum, we offered it to a sophomore class on digital logic design at a 4-year public university and collected pre- and post-assignment surveys to gauge understanding of the material. Reflection pieces were also used to evaluate the students' approach and level of comprehension. In this paper, we provide an overview of the BEADLE curriculum, and report on the results of its evaluation using a remotely accessible FPGA lab. Additionally, we highlight the various features integrated into the remote lab platform, aimed at enhancing students' understanding of the curriculum content. 
AU  - Rania Hussein
AU  - Riley Connor Maloney
AU  - Luis Rodriguez-Gil
AU  - Jon Ander Beroz
AU  - Pablo Orduna
CY  - Baltimore , Maryland
DA  - 2023/06/25
PB  - ASEE Conferences
TI  - RHL-BEADLE: Bringing Equitable Access to Digital Logic Design in Engineering Education
UR  - https://peer.asee.org/44147
DO  - 10.18260/1-2--44147
ER  -