Thompson, R., & Harris, D. L., & Stine, J., & Harris, S. L. (2025, June), RISC-V System-on-Chip Design Textbook and Course  Paper presented at 2025 ASEE Annual Conference & Exposition , Montreal, Quebec, Canada . 10.18260/1-2--57147

\bibitem{asee_peer_57147}
  Thompson, R., \& Harris, D. L., \& Stine, J., \& Harris, S. L. (2025, June), \emph{RISC-V System-on-Chip Design Textbook and Course}
  Paper presented at 2025 ASEE Annual Conference \& Exposition , Montreal, Quebec, Canada .
  10.18260/1-2--57147

Rose Thompson, David L Harris, James Stine Jr., and Sarah L Harris.  "RISC-V System-on-Chip Design Textbook and Course".  2025 ASEE Annual Conference & Exposition , Montreal, Quebec, Canada , 2025, June.  ASEE Conferences, 2025.  https://peer.asee.org/57147 Internet.  24 Aug, 2025

\bibitem{asee_peer_57147}
  Rose Thompson, David L Harris, James Stine Jr., and Sarah L Harris.
  "RISC-V System-on-Chip Design Textbook and Course".
  \emph{2025 ASEE Annual Conference \& Exposition , Montreal, Quebec, Canada , 2025, June}.
  ASEE Conferences, 2025.
  https://peer.asee.org/57147 Internet.  24 Aug, 2025

@INPROCEEDINGS{asee_peer_57147
author = "Rose Thompson, David L Harris, James Stine Jr., and Sarah L Harris"
title = "RISC-V System-on-Chip Design Textbook and Course"
booktitle = "2025 ASEE Annual Conference \& Exposition "
year = "2025"
month = "June"
address = "Montreal, Quebec, Canada "
publisher = "ASEE Conferences"
note = {https://peer.asee.org/57147}
number = {10.18260/1-2--57147}
}

TY  - CPAPER
AB  - We wrote a textbook, RISC-V System-on-Chip Design, to bridge the gap between learning about the theory of processor, computer architecture, and system-on-chip (SoC) design and being able to put these theories into practice by understanding, simulating, analyzing, and expanding a fully functional processor and SoC. The book begins with a brief history of processor design and an overview of the RISC-V architecture and then describes the tools needed to work with Wally, the open-source RISC-V SoC described in the book. These tools include GCC and the Sail, Spike, and Verilator simulators as well as best practices in hardware description language (HDL) design, design verification, and logic synthesis. The Wally SoC supports both of RISC-V’s base integer instruction sets, RV32I and RV64I, caches, branch prediction, virtual memory, and many extensions, including the compressed (C), multiply/divide (M), floating-point (Zfh/F/D/Q), atomic (A), and bit manipulation (B) extensions. Wally supports the RVI20U32, RVI20U64, and RVA22S64 RISC-V profiles and can boot Linux with privilege modes and virtual memory and can run on an FPGA. The textbook can be used to teach courses in computer architecture, SoC design, design verification, embedded systems, or a subset of these in theory, practice, or both. We describe two types of courses we taught using a draft version of this textbook: a senior/master’s level course that focused on all stages of SoC design and a second course taught at the sophomore/junior level that focused on computer architecture and processor design only. These courses used the labs, exercises, and Wally SoC that accompany the textbook. We expect this book and course, as well as Wally, to continue to evolve both in its capabilities and in the way that it is used and taught.
AU  - Rose Thompson
AU  - David L Harris
AU  - James Stine Jr.
AU  - Sarah L Harris
CY  - Montreal, Quebec, Canada 
DA  - 2025/06/22
PB  - ASEE Conferences
TI  - RISC-V System-on-Chip Design Textbook and Course
UR  - https://peer.asee.org/57147
DO  - 10.18260/1-2--57147
ER  -