Carroll, B. D., & Sharan, K. (2025, March), Teaching Digital Logic Design Using a Floating-Point Processor  Paper presented at 2025 ASEE -GSW Annual Conference, Arlington, TX, Texas. 10.18260/1-2--55081

\bibitem{asee_peer_55081}
  Carroll, B. D., \& Sharan, K. (2025, March), \emph{Teaching Digital Logic Design Using a Floating-Point Processor}
  Paper presented at 2025 ASEE -GSW Annual Conference, Arlington, TX, Texas.
  10.18260/1-2--55081

Bill D Carroll P.E. and Kartikey Sharan.  "Teaching Digital Logic Design Using a Floating-Point Processor".  2025 ASEE -GSW Annual Conference, Arlington, TX, Texas, 2025, March.  ASEE Conferences, 2025.  https://peer.asee.org/55081 Internet.  29 May, 2025

\bibitem{asee_peer_55081}
  Bill D Carroll P.E. and Kartikey Sharan.
  "Teaching Digital Logic Design Using a Floating-Point Processor".
  \emph{2025 ASEE -GSW Annual Conference, Arlington, TX, Texas, 2025, March}.
  ASEE Conferences, 2025.
  https://peer.asee.org/55081 Internet.  29 May, 2025

@INPROCEEDINGS{asee_peer_55081
author = "Bill D Carroll P.E. and Kartikey Sharan"
title = "Teaching Digital Logic Design Using a Floating-Point Processor"
booktitle = "2025 ASEE -GSW Annual Conference"
year = "2025"
month = "March"
address = "Arlington, TX, Texas"
publisher = "ASEE Conferences"
note = {https://peer.asee.org/55081}
number = {10.18260/1-2--55081}
}

TY  - CPAPER
AB  - Teaching Digital Logic Design Using a Floating-Point Processor
Kartikey Sharan and Bill Carroll
Computer Science and Engineering Department
The University of Texas at Arlington
This paper presents a comprehensive framework for incorporating the design and implementation of a 32-bit floating-point processing unit, developed as part of Kartikey Sharan’s master's thesis, into digital logic design courses. The project utilizes the SystemVerilog hardware description language and is implemented according to the IEEE 754 standard for single-precision floating-point operations. The pedagogical value of this project lies in its multifaceted approach to teaching digital logic principles through a real-world application, offering students hands-on experience with floating-point arithmetic, binary encoding, and Verilog simulation.
Currently, this project is being used in the Digital Logic Design II and Advanced Digital Logic Design courses at the University of Texas at Arlington, where it has been integrated as a capstone lab term project. We are in the process of collecting student feedback to refine its pedagogical impact and better tailor the learning experience.
The processor's architecture covers essential floating-point arithmetic operations, including addition, subtraction, multiplication, and division, each integrated with handling for overflow, underflow, and rounding operations. The design incorporates critical components such as a barrel shifter for efficient alignment and normalization tasks and a Wallace tree multiplier for high-speed multiplication, ensuring both performance and scalability.
The floating-point processor design offers students a valuable opportunity to work with core concepts in digital logic—such as binary encoding, floating-point representation, component synthesis, and simulation and verification—through a structured series of lab assignments. Each lab enables students to construct and simulate different processor components, such as mantissa shifters, exponent incrementors, and normalization units, building toward a fully functional floating-point processor. By adopting this model, educators can transform abstract theoretical principles into tangible skills, better preparing students to handle challenges in hardware architecture, precision arithmetic, and IEEE standards compliance.
Preliminary results on FPGA simulation platforms like ModelSim and Terasic’s DE10-Lite board have demonstrated the design’s accuracy and robustness, validating its efficacy as an educational tool. This project not only deepens students' understanding of digital logic design but also accelerates their familiarity with industry standards and best practices, making them more competitive in the job market. Educators who incorporate this floating-point processor into their curriculum can bridge the gap between theory and application, providing students with industry-relevant experience in a high-demand skill area.
Integrating this project into digital logic courses can transform traditional learning models, empowering students to navigate the complexities of high-precision digital systems with confidence, precision, and readiness for real-world applications.
The paper will include descriptions of component design and an overview of component integration leading to a complete floating-point processor.  Pedagogical experiences including successes and challenges will be described.  Finally, the paper will provide recommended changes for future use of the framework and underlying pedagogy.     

AU  - Bill D Carroll P.E.
AU  - Kartikey Sharan
CY  - Arlington, TX, Texas
DA  - 2025/03/09
PB  - ASEE Conferences
TI  - Teaching Digital Logic Design Using a Floating-Point Processor
UR  - https://peer.asee.org/55081
DO  - 10.18260/1-2--55081
ER  -