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Teaching Sequential Logic Circuit Vhdl Models By Synthesis And Examples

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Conference

2005 Annual Conference

Location

Portland, Oregon

Publication Date

June 12, 2005

Start Date

June 12, 2005

End Date

June 15, 2005

ISSN

2153-5965

Conference Session

Emerging Trends in Engineering Education Poster Session

Page Count

9

Page Numbers

10.1229.1 - 10.1229.9

Permanent URL

https://peer.asee.org/14230

Download Count

1847

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Paper Authors

author page

Guoping Wang

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Abstract
NOTE: The first page of text has been automatically extracted and included below in lieu of an abstract

Teaching Sequential Logic VHDL Models by Synthesis and Examples

Guoping Wang

Department of Engineering, Indiana University Purdue University Fort Wayne

Abstract

VHDL has become an industrial standard language in digital system design. This paper introduces the author’s experience in teaching sequential logic VHDL models to students through synthesis and examples from simple to complex design problems. The simple sequential circuits such as latches, FFs (flip-flops) are first introduced with all the control signals, then the same design concepts and procedures are extended to sequential logic blocks such as counters and shift registers. These design approaches are also applicable in complex sequential digital system designs. The author’s experiences showed the effectiveness of this approach in teaching sequential logic VHDL models.

Index term: Engineering course, VHDL, digital systems, sequential circuit.

Introduction

The VHSIC (very high speed integrated circuits) Hardware Description Language (VHDL) is a very powerful hardware language for digital system design. It has become indispensable in electrical and computer engineering programs.

Digital logic systems can be classified in combinational and sequential logic circuits. Sequential logic systems play a very important part. In teaching VHDL models of sequential logic circuits, the author found that students could easily get confused with all the different control signals, such as, CLOCK, ENABLE, RESET/SET, OVERFLOW, CARRY-OUT etc. Various VHDL teaching methods have been proposed in the past 1-7, however, how to teach sequential logic VHDL models more effectively has not been studied so far.

This paper introduces the author’s experience in teaching sequential logic VHDL models to students through synthesis and examples from simple to complex design problems. The simple sequential circuits such as latches, flip-flops are first introduced with all the control signals, then the same design concepts and procedures are extended to the designs of sequential logic blocks such as counters and shift registers. These design approaches are also applicable in complex sequential digital system designs. The author’s experiences showed the effectiveness of this approach in teaching sequential logic VHDL models. During the teaching process, both of the VHDL models and the synthesized circuits are introduced. This teaching approach is design-

Proceedings of the 2005 American Society for Engineering Education Annual Conference & Exposition Copyright ©2005, American Society for Engineering Education

Wang, G. (2005, June), Teaching Sequential Logic Circuit Vhdl Models By Synthesis And Examples Paper presented at 2005 Annual Conference, Portland, Oregon. https://peer.asee.org/14230

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