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Teaching the Hardware Implementation of Cybesecurity Encryption Algorithms on FPGA using Hands-on Projects

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Conference

2019 ASEE Annual Conference & Exposition

Location

Tampa, Florida

Publication Date

June 15, 2019

Start Date

June 15, 2019

End Date

June 19, 2019

Conference Session

Embedded Systems & Cybersecurity for ECE

Tagged Division

Electrical and Computer

Page Count

10

Permanent URL

https://peer.asee.org/33356

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Paper Authors

biography

Nader Rafla P.E. Boise State University

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Dr. Nader Rafla, P.E., received his MSEE and PhD. in Electrical Engineering from Case Western Reserve University, Cleveland, Ohio in 1984 and 1991 respectively. His Doctoral research concentrated on object recognition and localization from multi sensor data: range image, force-torque, and touch.
From 1991 to 1996, he was an Associate Professor at the Department of Manufacturing Engineering at Central State University. Where he taught courses was involved in collaborative research with Wright-Patterson Air Force in applied image processing.
In January 1997, he joined the newly developed electrical and computer engineering program at Boise State University where he is currently is the chair and an Associate professor. He led the development and starting of the BS and MS programs. He taught several courses and supervised numerous M.S. thesis and Senior Design Project. He contributed to the start of the PhD program and is currently advising three Ph.D. students and two MS students. He also has been conducting research and consultation in R&D for Micron Technology, Hewlett Packard and others.
Dr. Rafla’s areas of expertise are: security of systems on programmable chips and embedded systems; advanced methods for improving hardware and physical network security; evolvable hardware; and evolutionary and reconfigurable computing. He is a senior member of the IEEE organization and several societies, a member of the ASEE and ACM organizations.

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biography

H. Shelton Jacinto Boise State University

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H S. Jacinto received his B.S. degree in electrical and computer engineering from Boise State University, Boise, Idaho, USA, in 2017, and is currently a Ph.D. candidate in electrical and computer engineering from Boise State University, Boise, Idaho, USA. From 2015 to 2017 he worked with Idaho National Labs in conjunction with the Advanced Energy Lab conducting research on self-powered wireless sensor networks and their security. He has moved over to the Air Force Research Lab Quantum Information Science group in 2018 under a fellowship to work on quantum information processing systems, integrated quantum photonics, and quantum control. His main research focuses on quantum network hardware cybersecurity, quantum informatics, and adaptive hardware anti-tamper and encryption technologies for use in the field of hardware security to create a secure platform for an upcoming quantum era.

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biography

Luka Daoud Boise State University Orcid 16x16 orcid.org/https://0000-0003-4708-4718

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Luka Daoud received the B.S. degree in Electrical Engineering from Fayoum University, Egypt in 2007, and M.S. degree in Electronics and Communications Engineering from Egypt-Japan University of Science and Technology (E-JUST), Alexandria, Egypt in 2012. Luka is currently a Ph.D. candidate in Electrical and Computer Engineering at Boise State University, Boise, Idaho, USA. His main research focuses on hardware security, Network-on-Chip (NoC), high performance computing, and High Level Synthesis (HLS) design.

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Abstract

Cybersecurity is an important concept in today’s age of information and is of major interest to keep information secure, helping to protect sensitive information in the presence of untrusted third-parties. This has presented the need for an implemented hardware variant of secure algorithms with small footprint to help add protection while reducing processing time/overhead on a standard processor. In this work we present two hands-on projects that are designed specifically to teach these two concepts using project-based learning techniques in an innovative cooperative learning environment. The learning environment served to combine both student-peer learning and jigsaw strategies. The technical contents of the first project teach students the process and methodologies of designing and testing the hardware implementation of a block cipher encryption, the Advanced Encryption Standard, on a field-programmable gate array. The second project builds on the first by introducing the hardware implementation of hash message authentication codes through the Whirlpool hash function in three different operating modes. The objective of this work is to present an innovative teaching environment for these hands-on encryption algorithm-based projects using cooperative learning rather than a traditional mode of lecturing with given homework assignments. This environment encouraged students to think thoroughly, out-of-the-box, gain problem-solving skills, and improve their communication of technical concepts to peers through the delivery of student-led lectures. The assessment of student learning is accomplished by a mixture of presentations with peer evaluations, instructor evaluations, and thorough grading of project reports. End-of-course evaluations were positive regarding the learning environment and technical skills gained by students. For this work one assigned hands-on project for students working in groups resulted in unique per-group implementations, where in the second project, this led to different project perspectives and additions beyond a standard assigned project, enhanced by student-peer teaching. Students effectively learned and comprehended many different implementations of a widely used encryption and authentication algorithm via our modified teaching techniques.

Rafla, N., & Jacinto, H. S., & Daoud, L. (2019, June), Teaching the Hardware Implementation of Cybesecurity Encryption Algorithms on FPGA using Hands-on Projects Paper presented at 2019 ASEE Annual Conference & Exposition , Tampa, Florida. https://peer.asee.org/33356

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